HEF4020BT: 14-stage binary counter
The HEF4020B is a 14-stage binary counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to Q13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. A feature of the device is its high speed (typ. 35 MHz at VDD = 15 V).
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.
HEF4020BT: Product Block Diagram
sot109-1_3d
Data Sheets (1)
Application Notes (1)
Brochures (2)
Package Information (1)
Supporting Information (2)
Ordering Information
| Product | Status | Family | Function | VCC (V) | Output drive capability (mA) | Description | Logic switching levels | Package version | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|
| HEF4020BT | Active | HEF4000B | Binary counters/timers | 4.5 - 15.5 | +/- 2.4 | 14-stage binary ripple counter | CMOS | SOT109-1 | 35 | medium | -40~85 | 56 | 1.0 | 13 | SO16 | 16 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|
| HEF4020BT | | SOT109-1 | SO-SOJ-REFLOW
SO-SOJ-WAVE
SO-SOJ-REFLOW
SO-SOJ-WAVE | Reel 13" Q1/T1 CECC | Active | HEF4020BT,653
(9333 727 30653) | HEF4020BT | HEF4020BT |    | week 4, 2004 | 75.3 | 2.99 | 3.34E8 | 1 | 1 |
| Bulk Pack, CECC | Active | HEF4020BT,652
(9333 727 30652) | HEF4020BT | HEF4020BT | | week 4, 2004 | 75.3 | 2.99 | 3.34E8 | 1 | 1 |
