LPC3141FET180: ARM926EJ-S with 192 kB SRAM, USB High-speed OTG, SD/MMC, NAND flash controller
The NXP® LPC3141 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0 OTG, 192 kB SRAM, NAND flash controller, flexible external bus interface, four channel 10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets. To optimize system power consumption, the LPC3141 have multiple power domains and a very flexible Clock
sot570-3_3d
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-cost, low-power ARM926EJ microcontrollers with USB High-speed OTG, SD/MMC, and NAND flash controller (REV 1.0) PDF (597.0 kB) LPC3141_43 | 04 Jun 2012 |
Application Notes (3)
| Name/Description | Modified Date |
|---|---|
| Using the LCD interface in the LPC313x/LPC314x/LPC315x devices (REV 1.0) PDF (618.0 kB) AN10880 | 06 Mar 2015 |
| UUencoding for UART ISP (REV 1.0) PDF (139.0 kB) AN11229 | 06 Jul 2012 |
| PCB layout guidelines for NXP® MCUs in BGA packages (REV 2.0) PDF (272.0 kB) AN10778 | 22 Apr 2011 |
Users Guides (1)
| Name/Description | Modified Date |
|---|---|
| LPC314x User manual (REV 1.0) PDF (2.6 MB) UM10362 | 11 Dec 2012 |
Brochures (1)
| Name/Description | Modified Date |
|---|---|
| Lowest Cost ARM9 with HS USB 2.0 OTG & Decryption Engine (REV 1.0) PDF (540.0 kB) LPC3141ANDLPC3143 | 01 May 2009 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| thin fine-pitch ball grid array package; 180 balls (REV 1.0) PDF (536.0 kB) SOT570-3 | 08 Feb 2016 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| ADC design guidelines (REV 1.0) PDF (145.0 kB) TN00009 | 09 May 2014 |
Ordering Information
| Product | Status | Core | Clock speed [max] (MHz) | DMIPS | Flash (kB) | RAM (kB) | EEPROM (kB) | GPIO | Ethernet | USB | USB (speed) | USB (type) | LCD | CAN | UART | I²C | SPI | I²S | ADC channels | ADC (bits) | SCTimer / PWM | DAC (bits) | Timers | Timer (bits) | RTC | PWM | QEI | IOH | Package name | Temperature range | Supply voltage [min] (V) | Supply voltage [max] (V) | Demoboard | Product category |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LPC3141FET180 | Active | ARM9 | 270 | 192 | 97 | 2 | 1 | 2 | 1 | 2 | 4 | 10 | 1 | 4 | 32 | 1 | N | TFBGA180 | -40 °C to +85 °C | 1.8 | 3.3 | OM11037 | 170-LPC3100/200- |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LPC3141FET180 | | SOT570-3 | Tray, Bakeable, Single in Drypack | Active | LPC3141FET180,551 (9352 897 11551) | Standard Marking | LPC3141FET180 |    | Always Pb-free | NA | 3 |
- Using the LCD interface in the LPC313x/LPC314x/LPC315x devices LPC3154FET208
- UUencoding for UART ISP LPC43S50FET256
- PCB layout guidelines for NXP® MCUs in BGA packages LPC4350FET256
- LPC314x User manual LPC3143FET180
- Lowest Cost ARM9 with HS USB 2.0 OTG & Decryption Engine LPC3143FET180
- ADC design guidelines LPC4333JET256
- SOT570-3 LPC43S50FET180
- LPC3143FET180
