NPIC6C596BQ: Power logic 8-bit shift register; open-drain outputs

The NPIC6C596 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. To provide additional hold time in cascaded applications, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the storage register drives the gate of the output extended-drain NMOS (EDNMOS) transistor whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers.

The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS transistors designed for use in systems that require moderate load power such as LEDs. Integrated voltage clamps in the outputs provide protection against inductive transients making the device suitable for power driver applications such as relays, solenoids and other low-current or medium-voltage loads.

NPIC6C596BQ: Product Block Diagram

Outline 3d SOT763-1

Data Sheets (1)

Name/Description	Modified Date
Power logic 8-bit shift register; open-drain outputs (REV 2.0) PDF (1.3 MB) NPIC6C596 [English]	04 Jul 2013

Brochures (2)

Name/Description	Modified Date
NXP® NPIC shift register based LED drivers (REV 2.0) PDF (523.0 kB) 75017648 [English]	13 May 2015
Using shift registers to reduce size and BOM in LED designs (REV 1.0) PDF (705.0 kB) 75017624_1 [English]	20 Nov 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x... (REV 1.1) PDF (191.0 kB) SOT763-1 [English]	30 May 2016

Packing (1)

Name/Description	Modified Date
DHVQFN16; Reel pack, SMD, 7" Q1/T1 standard product orientation Orderable part number ending ,115 or... (REV 2.0) PDF (191.0 kB) SOT763-1_115 [English]	05 Jul 2016

Ordering Information

Product	Status	Family	V_CC (V)	Function	Logic switching levels	Description	Package version	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
NPIC6C596BQ	Active	NPIC	4.5 - 5.5	Shift registers	CMOS	8-bit serial-in/serial or parallel-out shift register with output register LED driver (3-state)	SOT763-1	100	90	10	8	low	-40~125	86	9.0	54	DHVQFN16	16