PCA9525D: Simple 2-wire bus buffer
The PCA9525 is a monolithic CMOS integrated circuit for bus buffering in applications including I²C-bus, SMBus, DDC, PMBus, and other systems based on similar principles.
The buffer extends the bus load limit by buffering both the SCL and SDA lines, allowing the maximum permissible bus capacitance on both sides of the buffer.
The PCA9525 includes a unidirectional buffer for the clock signal, and a bidirectional buffer for the data signal. Slave devices which employ clock stretching are therefore not supported.
In its most basic implementation, the buffer will allow an extended number of slave devices to be attached to one (or more) master devices. In this case, all master devices would be positioned on the Sxx_IN side of the PCA9525.
The direction pin (DIR) further enhances this function by allowing the unidirectional clock signal to be reversed, thus allowing master devices on both sides of the buffer.
The enable (EN) function allows sections of the bus to be isolated. Individual parts of the system can be brought on-line successively. This means a controlled start-up using a diverse range of components, operating speeds and loads is easily achieved.
PCA9525D: Product Block Diagram
sot096-1_3d
Data Sheets (1)
Users Guides (3)
Brochures (1)
Package Information (1)
Packing (1)
Supporting Information (3)
IBIS Model
Ordering Information
| Product | Status | Package version | Application | Reset input pin | Function | Operating Temperature (Cel) | Number of bits | I2C-bus (kHz) | Operating voltage (VDC) | Operating voltage 2 (V) | Inputs | Outputs | Max Sink Current per bit (mA) | No of Addresses | Voltage Translation Range (V) | Max Sink Current, per package (mA) | Enable |
|---|
| PCA9525D | End of Life | SOT96-1 | | | | -40~85 | | 1000 | 2.7~5.5 | | 1 | 1 | | | | | |
Package Information
