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MC100E210: 5.0 V ECL Dual 1:4, 1:5 Differential Clock/Data Fanout Buffer

The MC100E210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part-to-part skew down to an output-to-output skew. This capability reduces the skew by a factor of 4 as compared to using twoLVE111's to accomplish the same task.The lowest tpd delay time results from terminating only one output pair, and the greatest tpd delay time results from terminating all the output pairs. This shift is about 10-20 pS in tpd. The skew between any two output pairs within a device is typically about 25 nS. If other output pairs are not terminated, the lowest tpd delay time results from both output pairs and the skew is typically 25 nS. When all outputs are terminated, the greatest tpd (delay time) occurs and all outputs display about the same 10-20 pS increase in tpd, so the relative skew between any two output pairs remains about 25 nS.For more information on using PECL, designers should refer to Application Note AN1406/D.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

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