MC100EL1648: Voltage Controlled Oscillator, ECL, 5.0 V

The MC100EL1648 requires an external parallel tank circuit consisting of the inductor (L) and capacitor (C). A varactor diode may be incorporated into the tank circuit to provide a voltage variable input for the oscillator (VCO). This device may also be used in many other applications requiring a fixed frequency clock. The MC100EL1648 is ideal in applications requiring a local oscillator. Systems include electronic test equipment and digital high-speed telecommunications.The MC100EL1648 is based on the VCO circuit topology of the MC1648. The MC100EL1648 uses advanced bipolar process technology which results in a design which can operate at an extended frequency range.The ECL output circuitry of the MC100EL1648 is not a traditional open emitter output structure and instead has an on-chip termination resistor with a nominal value of 510 ohms. This facilitates direct ac-coupling of the output signal into a transmission line. Because of this output configuration, an external pull-down resistor is not required to provide the output with a dc current path. This output is intended to drive one ECL load. If the user needs to fanout the signal, an ECL buffer such as the MC10EL16 Line Receiver/Driver should be used NOTE: The MC100EL1648 is NOT useable as a crystal oscillator.

Features
  • Typical Operating Frequency Up to 1100 MHz
  • Low-Power 19 mA at 5.0 Vdc Power Supply
  • Phase Noise -90 dBc/Hz at 25 kHz Typical
  • ESD Protection: >2 KV HBM, >100 V MM
  • PECL Mode Operating Range: VCC= 5.0 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -5.2 V
  • Input Capacitance= 6.0 pF (TYP)
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Maximum Series Resistance for L (External Inductance)= 50 W (TYP)
  • Moisture Sensitivity Level 1. For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8?, Oxygen Index 28 to 34
  • Transistor Count = 11 devices
  • Pb-Free Packages are Available
Application Notes (17)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS and ECLinPS Lite SPICE I/O Modeling KitAN1503/D (120.0kB)6
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Package Drawings (2)
Document TitleDocument ID/SizeRevision
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
5V ECL Voltage Controlled OscillatorMC100EL1648/D (215.0kB)8
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EL1648DGActivePb-freeSOIC-8751-071Tube98Contact BDTIC
MC100EL1648DTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
MC100EL1648DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
Specifications
ProductInput LevelOutput LevelfMax Typ (MHz)VCC Typ (V)Duty Cycle (%)
MC100EL1648DGECLECL11005.550
MC100EL1648DTGECLECL11005.550
MC100EL1648DTR2GECLECL11005.550
5V ECL Voltage Controlled Oscillator (215.0kB) MC100EL1648
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit MC100EP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L