MC100EL29: 5.0 V ECL Dual Differential Clock / Data D Flip-Flop With Set and Reset
The MC100EL29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE and the Dbar input will bias around VCC/2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up.Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.
特性- 1100 MHz Flip-Flop Toggle Frequency
- 580 ps Propagation Delays
- ESD Protection: > 2 kV HBM, > 100 V MM
- Q Output will Default LOW with Inputs Open or at VEE
- The 100 Series Contains Temperature Compensation
- PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
- Internal Input Pulldown Resistors on D(s), CLK(s), S(s), and R(s).
- Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
- Flammability Rating: UL-94 code V-0 @ 0.125 in, Oxygen Index 28 to 34
- Transistor Count = 313 devices
- Pb-Free Packages are Available
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应用注释 (17)
数据表 (1)
仿真模型 (1)
封装图纸 (1)
Document Title | Document ID/Size | Revision |
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SOIC-20 WB | 751D-05 (36.3kB) | H |
产品订购型号
产品 | 状况 | Compliance | 具体说明 | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价) |
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MC100EL29DWG | Active | Pb-free
Halide free | 5.0 V ECL Dual Differential Clock / Data D Flip-Flop With Set and Reset | SOIC-20W | 751D-05 | 3 | Tube | 38 | 联系BDTIC |
MC100EL29DWR2G | Active | Pb-free
Halide free | 5.0 V ECL Dual Differential Clock / Data D Flip-Flop With Set and Reset | SOIC-20W | 751D-05 | 3 | Tape and Reel | 1000 | 联系BDTIC |
订购产品技术参数
Product | Type | Bits | Input Level | Output Level | VCC Typ (V) | tJitter Typ (ps) | tpd Typ (ns) | tsu Min (ns) | th Min (ns) | trec Typ (ns) | tR & tF Max (ps) | fToggle Typ (MHz) |
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MC100EL29DWG | D-Type | 2 | ECL
LVDS | ECL | 5 | 1 | 0.6 | 0 | 0.1 | 0.1 | 550 | 1100 |
MC100EL29DWR2G | D-Type | 2 | ECL
LVDS | ECL | 5 | 1 | 0.6 | 0 | 0.1 | 0.1 | 550 | 1100 |