MC100EP139: 3.3 V / 5.0 V ECL ÷·2/4, ÷·4/5/6 Clock Generator Chip

The MC10/100EP139 is a low skew divide by 2/4, divide by 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLKbar input and bypassed to ground via a 0.01uF capacitor.The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple EP139s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one EP139, the MR pin need not be exercised as the internal divider design ensures synchronization between the divide by 2/4 and the divide by 4/5/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation.The 100 Series contains temperature compensation.

Features
  • Maximum Frequency >1.0 GHz Typical
  • 50ps Output-to-Output Skew
  • PECL Mode Operating Range: VCC=3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Synchronous Enable/Disable
  • Master Reset for Synchronization of Multiple Chips
  • VBB Output
  • Pb-Free Packages are Available
Applications
  • Low-Clock Skew Generation
Application Notes (17)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS and ECLinPS Lite SPICE I/O Modeling KitAN1503/D (120.0kB)6
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V / 5 V ECL Divide by 2/4, Divide by 4/5/6 Clock Generation ChipMC10EP139/D (212kB)14Aug, 2016
Simulation Models (5)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100EP139DT 3.3 VMC100EP139DT_33.IBS (13.0kB)4
IBIS Model for MC100EP139DT 5.0 VMC100EP139DT_50.IBS (14.0kB)3
IBIS Model for MC100EP139DT VEE -3.3 VMC100EP139DT_-33.IBS (13.0kB)3
IBIS Model for MC100EP139DT for -5.2VMC100EP139DT_-52.IBS (14.0kB)3
IBIS Model for mc100ep139dw at 3.3VMC100EP139DW_33.IBS (12.0kB)2
Package Drawings (3)
Document TitleDocument ID/SizeRevision
QFN20, 4x4, 0.5P485E-01 (60.9kB)B
SOIC-20 WB751D-05 (36.3kB)H
TSSOP-20 WB948E-02 (39.7kB)D
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EP139DTGActivePb-free Halide freeTSSOP-20948E-021Tube75Contact BDTIC
MC100EP139DTR2GActivePb-free Halide freeTSSOP-20948E-021Tape and Reel2500Contact BDTIC
MC100EP139DWGActivePb-free Halide freeSOIC-20W751D-053Tube38Contact BDTIC
MC100EP139DWR2GLifetimePb-free Halide freeSOIC-20W751D-053Tape and Reel1000
MC100EP139MNGActivePb-free Halide freeQFN-20485E-011Tube92Contact BDTIC
MC100EP139MNTXGLifetimePb-free Halide freeQFN-20485E-011Tape and Reel3000
Specifications
ProductTypeInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100EP139DTGDividerECL CMLECL5 3.310000.75250
MC100EP139DTR2GDividerECL CMLECL5 3.310000.75250
MC100EP139DWGDividerCML ECLECL3.3 510000.75250
MC100EP139MNGDividerECL CMLECL3.3 510000.75250
3.3 V / 5 V ECL Divide by 2/4, Divide by 4/5/6 Clock Generation Chip (212kB) MC10EP139
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit MC100EP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100EP139DT 3.3 V MC100EP139
IBIS Model for MC100EP139DT 5.0 V MC100EP139
IBIS Model for MC100EP139DT VEE -3.3 V MC100EP139
IBIS Model for MC100EP139DT for -5.2V MC100EP139
IBIS Model for mc100ep139dw at 3.3V MC100EP139
TSSOP-20 WB NLSX3018
SOIC-20 WB NLSX3018
QFN20, 4x4, 0.5P MC10EP57