MC100EP140: Phase-Frequency Detector, 3.3 V, ECL

The MC100EP140 is a three state phase frequency-detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Since the part is designed with fully differential gates, the noise is reduced throughout the circuit, especially at high speeds. The basic operation of a Phase/Frequency Detector (PFD) is to "compare" an incoming signal (feedback) to a set reference signal. When the Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase, the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO.The device is packaged in a small outline, surface mount 8-lead SOIC package. The output of the EP140 is 400 mV, which allows faster switching time and greater bandwidth. This device can also be used in +3.3 V systems. For proper operation, the input edge rate of the R and FB inputs should be less than 5 ns.More information on Phase Lock Loop operation and application can be found in AND8040.

Features
  • 500 ps Typical Propagation Delay
  • Maximum Frequency > 2.1 Ghz Typical
  • Fully Differential Internally
  • Advanced High Band Output Swing of 400 mV
  • Transfer Gain: 1.0 mV/Degree at 1.4 GHz, 1.2 mV/Degree at 1.0 GHz
  • Rise and Fall Time: 100 ps Typical
  • The 100 Series Contains Temperature Compensation
  • PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
  • Open Input Default State
  • Pb-Free Packages are Available
Application Notes (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
Phase-Frequency Detector, 3.3 V, ECLMC100EP140/D (117.0kB)9
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
ECLinPS Plus SPICE Modeling KitAND8009 (343.0kB)11
IBIS Model for MC100EP140D 3.3VMC100EP140D_33.IBS (10.0kB)3
Package Drawings (1)
Document TitleDocument ID/SizeRevision
SOIC-8 Narrow Body751-07 (62.6kB)AK
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EP140DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
MC100EP140DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500Contact BDTIC
Specifications
ProductInput LevelOutput LevelVCC Typ (V)Transfer Gain Typ (mV/degree)CMRR Max (V)fToggle Max (MHz)tpd Typ (ns)tJitter Typ (ps)tR & tF Max (ps)
MC100EP140DGCML ECLECL3.31.207320000.4750.2200
MC100EP140DR2GECL CMLECL3.31.207320000.4750.2200
Phase-Frequency Detector, 3.3 V, ECL (117.0kB) MC100EP140
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
ECLinPS Plus SPICE Modeling Kit NB4N840M
IBIS Model for MC100EP140D 3.3V MC100EP140
SOIC-8 Narrow Body CM1216