MC100EP142: ECL 9-Bit Shift Register _ BDTIC a Leading Distributor in China

MC100EP142: ECL 9-Bit Shift Register

The MC10EP/100EP142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 - D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.The SEL (Select) input pin is used to switch between the two modes of operation - SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK0 or CLK1; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the resisters to zero.The 100 Series contains temperature compensation.

Features

> 3 GHz Minimum Shift Frequency
9-Bit for Byte-Parity Applications
Asynchronous Master Reset
Dual Clocks
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –5.5 V
Open Input Default State
Safety Clamp on Inputs

Applications

Byte parity

Application Notes (14)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3V / 5V ECL 9-Bit Shift Register	MC10EP142/D (127kB)	18

Simulation Models (1)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for MC100EP142FA 3.3V	MC100EP142FA_33V.IBS (6.0kB)	1

Package Drawings (1)

Document Title	Document ID/Size	Revision
QFN32, 5x5, 0.5P, 3.1x3.1EP	488AM (57.4kB)	A

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
MC100EP142FAG	Active	Pb-free Halide free	LQFP-32	Contact BDTIC	2	Tray JEDEC	250	Contact BDTIC
MC100EP142FAR2G	Active	Pb-free Halide free	LQFP-32	Contact BDTIC	2	Tape and Reel	2000	Contact BDTIC
MC100EP142MNG	Active	Pb-free Halide free	QFN-32	488AM	1	Tube	74	Contact BDTIC
MC100EP142MNR4G	Lifetime	Pb-free Halide free	QFN-32	488AM	1	Tape and Reel	1000

Specifications

Product	Type	Bits	Input Level	Output Level	VCC Typ (V)	tJitter Typ (ps)	tpd Typ (ns)	tsu Min (ns)	th Min (ns)	trec Typ (ns)	tR & tF Max (ps)	fToggle Typ (MHz)
MC100EP142FAG	Shift Register	9	CML ECL	ECL	3.3 5	1	0.675	0.05	0.1	0.8	250	2800
MC100EP142FAR2G	Shift Register	9	CML ECL	ECL	3.3 5	1	0.675	0.05	0.1	0.8	250	2800
MC100EP142MNG	Shift Register	9	ECL CML	ECL	3.3 5	1	0.675	0.05	0.1	0.8	250	2800