MC100EP142: ECL 9-Bit Shift Register

The MC10EP/100EP142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 - D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.The SEL (Select) input pin is used to switch between the two modes of operation - SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK0 or CLK1; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the resisters to zero.The 100 Series contains temperature compensation.

Features
  • > 3 GHz Minimum Shift Frequency
  • 9-Bit for Byte-Parity Applications
  • Asynchronous Master Reset
  • Dual Clocks
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
Applications
  • Byte parity
Application Notes (14)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V / 5V ECL 9-Bit Shift RegisterMC10EP142/D (127kB)18
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100EP142FA 3.3VMC100EP142FA_33V.IBS (6.0kB)1
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN32, 5x5, 0.5P, 3.1x3.1EP488AM (57.4kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EP142FAGActivePb-free Halide freeLQFP-32Contact BDTIC2Tray JEDEC250Contact BDTIC
MC100EP142FAR2GActivePb-free Halide freeLQFP-32Contact BDTIC2Tape and Reel2000Contact BDTIC
MC100EP142MNGActivePb-free Halide freeQFN-32488AM1Tube74Contact BDTIC
MC100EP142MNR4GLifetimePb-free Halide freeQFN-32488AM1Tape and Reel1000
Specifications
ProductTypeBitsInput LevelOutput LevelVCC Typ (V)tJitter Typ (ps)tpd Typ (ns)tsu Min (ns)th Min (ns)trec Typ (ns)tR & tF Max (ps)fToggle Typ (MHz)
MC100EP142FAGShift Register9CML ECLECL3.3 510.6750.050.10.82502800
MC100EP142FAR2GShift Register9CML ECLECL3.3 510.6750.050.10.82502800
MC100EP142MNGShift Register9ECL CMLECL3.3 510.6750.050.10.82502800
3.3V / 5V ECL 9-Bit Shift Register (127kB) MC10EP142
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100EP142FA 3.3V MC100EP142
QFN32, 5x5, 0.5P, 3.1x3.1EP NCN6804