MC100EP16T: Differential Driver / Receiver with Internal Termination

The EP16T is a world-class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 resistor is connected from the D input to the VT pin and from the Dbar input to the VTbar pin. Tie the VT and VTbar pins to VTT supply (VCC - 2 V) for parallel termination or connect VT and VTbar pins for 100 input series termination.Special considerations are required for differential inputs under No Signal conditions to prevent instability.The 100 Series contains temperature compensation.

Features
  • 220 ps Typical Propagation Delay
  • Maximum Frequency > 3 GHz Typical
  • PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V
  • Internal 50 Ω Termination Resistors
Applications
  • Low-Clock Skew
Application Notes (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V / 5 V ECL Differential Receiver/Driver with Internal TerminationMC10EP16T/D (185kB)7Jul, 2016
Simulation Models (3)
Document TitleDocument ID/SizeRevisionRevision Date
IBS Model for MC100EP16DT 3.3VMC100EP16DT_33.IBS (5.0kB)2
IBIS Model for mc100ep16d 5.0VMC100EP16D_50.IBS (5.0kB)2
IBIS Model for mc100ep16dt 5.0VMC100EP16DT_50.IBS (5.0kB)2
Package Drawings (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EP16TDGLast ShipmentsPb-free Halide freeSOIC-8751-071Tube98
MC100EP16TDR2GLifetimePb-free Halide freeSOIC-8751-071Tape and Reel2500
MC100EP16TDTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
MC100EP16TDTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
MC100EP16TMNR4GLifetimePb-free Halide freeDFN-8506AA1Tape and Reel1000
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100EP16TDTGSignal Driver11:1CML ECLECL5 3.30.2200.241703000
MC100EP16TDTR2GSignal Driver11:1CML ECLECL5 3.30.2200.241703000
3.3 V / 5 V ECL Differential Receiver/Driver with Internal Termination (185kB) MC10EP16T
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBS Model for MC100EP16DT 3.3V MC100EP16VT
IBIS Model for mc100ep16d 5.0V MC100EP16VT
IBIS Model for mc100ep16dt 5.0V MC100EP16VT
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220
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