MC100EP16VC: Differential Driver / Receiver with High Gain and Enable Output
The EP16VC is a world-class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain and enable output.The EP16VC provides an ENbar input which is synchronized with the data input (D) signal in a way that provides litchless gating of the QHG and QHGbar outputs.When the ENbar signal is LOW, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and ENbar goes HIGH, it will force the QHG LOW and the QHGbar HIGH on the next negative transition of the data input. If the data input is LOW when the ENbar goes HIGH, the next data transition to a HIGH is ignored and QHG remains LOW and QHGbar remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The QHG and QHGbar outputs remain in their disabled state as long as the ENbar input is held HIGH or LOW. The ENbar input has no influence on the Qbar output and the data input is passed on (inverted) to this output whether ENbar is HIGH or LOW. This configuration is ideal for crystal oscillator applications where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The 100 Series contains temperature compensation.
Features- 310 ps Typical Prop Delay Qbar, 380 ps Typical Prop Delay QHG, QHGbar
- Gain > 200
- Maximum Frequency > 3 GHz Typical
- PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –5.5 V
- Open Input Default State
- QHG Output Will Default LOW with D inputs Open or at VEE
- VBB Output
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Application Notes (15)
Data Sheets (1)
Simulation Models (3)
Package Drawings (3)
Order Information
Product | Status | Compliance | Package | MSL* | Container | Budgetary Price/Unit |
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MC100EP16VCDG | Active | Pb-free
Halide free | SOIC-8 | 751-07 | 1 | Tube | 98 | Contact BDTIC |
MC100EP16VCDR2G | Lifetime | Pb-free
Halide free | SOIC-8 | 751-07 | 1 | Tape and Reel | 2500 | |
MC100EP16VCDTG | Last Shipments | Pb-free
Halide free | TSSOP-8 | 948R-02 | 3 | Tube | 100 | |
MC100EP16VCDTR2G | Active | Pb-free
Halide free | TSSOP-8 | 948R-02 | 3 | Tape and Reel | 2500 | Contact BDTIC |
MC100EP16VCMNR4G | Lifetime | Pb-free
Halide free | DFN-8 | 506AA | 1 | Tape and Reel | 1000 | |
Specifications
Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
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MC100EP16VCDG | Signal Driver | 1 | 1:2 | ECL | ECL | 5
3.3 | 0.2 | 20 | 0.38 | 400 | 3000 | |
MC100EP16VCDTR2G | Signal Driver | 1 | 1:2 | ECL | ECL | 5
3.3 | 0.2 | 20 | 0.38 | 400 | 3000 | |