MC100EP17: Quad Differential Driver / Receiver

The MC10/100EP17 is a 4-bit differential line receiver based on the EP16 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. Inputs of unused gates can be left open and will not affect the operation of the rest of the device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100 Series contains temperature compensation.

Features
  • 220 ps Typical Propagation Delay
  • Maximum Frequency >3.0 GHz Typical
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Output Will Default LOW with Inputs Open or at VEE
  • VBB Output
Applications
  • Ideal for buffering high speed oscillators
Application Notes (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V/5 V ECL Quad Differential Driver/ReceiverMC10EP17/D (120kB)10Dec, 2016
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for mc100ep17dt 3.3VMC100EP17DT_33.IBS (7.0kB)1
IBIS Model for mc100ep17dt at -5.2 VEEMC100EP17DT_-52.IBS (7.0kB)1
Package Drawings (3)
Document TitleDocument ID/SizeRevision
QFN20, 4x4, 0.5P485E-01 (60.9kB)B
SOIC-20 WB751D-05 (36.3kB)H
TSSOP-20 WB948E-02 (39.7kB)D
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EP17DTGActivePb-free Halide freeTSSOP-20948E-021Tube75Contact BDTIC
MC100EP17DTR2GLifetimePb-free Halide freeTSSOP-20948E-021Tape and Reel2500
MC100EP17DWGActivePb-free Halide freeSOIC-20W751D-053Tube38Contact BDTIC
MC100EP17DWR2GLifetimePb-free Halide freeSOIC-20W751D-053Tape and Reel1000
MC100EP17MNGLast ShipmentsPb-free Halide freeQFN-20485E-011Tube92
MC100EP17MNTXGLast ShipmentsPb-free Halide freeQFN-20485E-011Tape and Reel3000
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100EP17DTGSignal Driver41:1ECL CMLECL5 3.30.1470.222203000
MC100EP17DWGSignal Driver41:1CML ECLECL5 3.30.1470.222203000
3.3 V/5 V ECL Quad Differential Driver/Receiver (120kB) MC10EP17
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for mc100ep17dt 3.3V MC100EP17
IBIS Model for mc100ep17dt at -5.2 VEE MC100EP17
TSSOP-20 WB NLSX3018
SOIC-20 WB NLSX3018
QFN20, 4x4, 0.5P MC10EP57
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