MC100EP210S: Clock Driver, 1:5 Differential, Dual LVDS, 2.5 V

The MC100EP210S is a low skew 1-to-5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to five identical differential LVDS outputs. The EP210S specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. Two internal 50-ohm resistors are provided across the inputs. For LVDS inputs, VTA and VTB pins should be unconnected. For LVPECL inputs, VTA and VTB pins should be connected to the VTT (VCC - 2.0 V) supply. Designers can take advantage of the EP210S performance to distribute low skew LVDS clocks across the backplane or the board. Special considerations are required for differential inputs under No Signal conditions to prevent instability.

Features
  • 20 ps Typical Output-to-Output Skew
  • 85 ps Typical Device-to-Device Skew
  • 550 ps Typical Propagation Delay
  • The 100 Series contains temperature compensation.
  • Maximum Frequency > 1 Ghz
  • Operating Range: VCC = 2.375 V to 2.625 V with VEE = 0 V
  • Internal 50Ω Input Termination Resistors
  • LVDS Input/Output Compatible
  • Pb-Free Packages are Available
Applications
  • High Performance Logic for test systems and work stations. Clock fan out in routers, switches and other networking applications
Application Notes (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5V 1:5 Dual Differential LVDS Clock DriverMC100EP210S/D (138.0kB)10
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
ECLinPS Plus SPICE Modeling KitAND8009 (343.0kB)11
IBIS Model for mc100ep210sfa 2.5 VCCMC100EP210SFA_25.IBS (28.0kB)4
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN32, 5x5, 0.5P, 3.1x3.1EP488AM (57.4kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EP210SFAGActivePb-free Halide freeLQFP-32Contact BDTIC2Tray JEDEC250Contact BDTIC
MC100EP210SFAR2GActivePb-free Halide freeLQFP-32Contact BDTIC2Tape and Reel2000Contact BDTIC
MC100EP210SFATWGLifetimePb-free Halide freeLQFP-32Contact BDTIC2Tape and Reel2000
MC100EP210SMNGActivePb-free Halide freeQFN-32488AM1Tube74Contact BDTIC
MC100EP210SMNR4GActivePb-free Halide freeQFN-32488AM1Tape and Reel1000Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100EP210SFAGBuffer21:5CML ECL LVDSLVDS2.50.2250.552001000
MC100EP210SFAR2GBuffer21:5ECL CML LVDSLVDS2.50.2250.552001000
MC100EP210SMNGBuffer21:5ECL LVDS CMLLVDS2.50.2250.552001000
MC100EP210SMNR4GBuffer21:5LVDS ECL CMLLVDS2.50.2250.552001000
2.5V 1:5 Dual Differential LVDS Clock Driver (138.0kB) MC100EP210S
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
ECLinPS Plus SPICE Modeling Kit NB4N840M
IBIS Model for mc100ep210sfa 2.5 VCC MC100EP210S
QFN32, 5x5, 0.5P, 3.1x3.1EP NCN6804