MC100EP29: ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset

The MC10/100EP29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC10/100EP29 is functionally equivalent to the MC10/100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input.The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the Dbar input will pull down to VEE and the Dbar input will bias around VCC/2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up.Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The 100 Series Contains Temperature Compensation

Features
  • Maximum Frequency > 3 GHz Typical
  • 500 ps Typical Propagation Delays
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • These are Pb−Free Devices
Applications
  • Functionally equivalent to the MC10/100EL29
Application Notes (14)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and ResetMC10EP29/D (105kB)9Apr, 2014
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS MODEL FOR MC100EP29DT 3.3VMC100EP29DT_33.IBS (6.0kB)3
IBIS Model for MC100EP29DT with VEE at -5.2 VMC100EP29DT_-52.IBS (6.0kB)1
Package Drawings (2)
Document TitleDocument ID/SizeRevision
QFN20, 4x4, 0.5P485E-01 (60.9kB)B
TSSOP-20 WB948E-02 (39.7kB)D
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EP29DTGActivePb-free Halide freeTSSOP-20948E-021Tube75Contact BDTIC
MC100EP29DTR2GActivePb-free Halide freeTSSOP-20948E-021Tape and Reel2500Contact BDTIC
MC100EP29MNGActivePb-free Halide freeQFN-20485E-011Tube92Contact BDTIC
MC100EP29MNTXGActivePb-free Halide freeQFN-20485E-011Tape and Reel3000Contact BDTIC
Specifications
ProductTypeBitsInput LevelOutput LevelVCC Typ (V)tJitter Typ (ps)tpd Typ (ns)tsu Min (ns)th Min (ns)trec Typ (ns)tR & tF Max (ps)fToggle Typ (MHz)
MC100EP29DTGD-Type2ECL CMLECL3.3 50.20.420.10.10.082503000
MC100EP29DTR2GD-Type2ECL CMLECL3.3 50.20.420.10.10.082503000
MC100EP29MNGD-Type2ECL CMLECL5 3.30.20.420.10.10.082503000
MC100EP29MNTXGD-Type2CML ECLECL3.3 50.20.420.10.10.082503000
3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset (105kB) MC10EP29
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS MODEL FOR MC100EP29DT 3.3V MC100EP29
IBIS Model for MC100EP29DT with VEE at -5.2 V MC100EP29
TSSOP-20 WB NLSX3018
QFN20, 4x4, 0.5P MC10EP57