MC100EP31: ECL D Flip-Flop with Set and Reset _ BDTIC a Leading Distributor in China

MC100EP31: ECL D Flip-Flop with Set and Reset

The MC10/100EP31 is a D flip-flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when CLK is low and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK.The 100 Series contains temperature compensation.

Features

340ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC= 3.0 V to 5.5 Vwith VEE= 0 V
NECL Mode Operating Range: VCC= 0 Vwith VEE= –3.0 V to –5.5 V
Open Input Default State
Q Output will default LOW with inputs open or at VEE
Pb-Free Packages are Available

Applications

Clock Distribution

Application Notes (16)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3 V / 5V ECL D Flip-Flop with Set and Reset	MC10EP31/D (177kB)	11	Aug, 2016

Simulation Models (1)

Document Title	Document ID/Size	Revision	Revision Date
IBS Model for MC100EP31DT_33	MC100EP31DT_33.IBS (5.0kB)	2

Package Drawings (3)

Document Title	Document ID/Size	Revision
DFN8 2.0x2.0x0.9mm, 0.5p	506AA (31.8kB)	F
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
MC100EP31DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	Contact BDTIC
MC100EP31DR2G	Lifetime	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500
MC100EP31DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	Contact BDTIC
MC100EP31DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	Contact BDTIC
MC100EP31MNR4G	Last Shipments	Pb-free Halide free	DFN-8	506AA	1	Tape and Reel	1000

Specifications

Product	Type	Bits	Input Level	Output Level	VCC Typ (V)	tJitter Typ (ps)	tpd Typ (ns)	tsu Min (ns)	th Min (ns)	trec Typ (ns)	tR & tF Max (ps)	fToggle Typ (MHz)
MC100EP31DG	D-Type	1	ECL CML	ECL	5 3.3	0.2	0.34	0.1	0.15	0.225	180	3000
MC100EP31DTG	D-Type	1	CML ECL	ECL	3.3 5	0.2	0.34	0.1	0.15	0.225	180	3000
MC100EP31DTR2G	D-Type	1	CML ECL	ECL	5 3.3	0.2	0.34	0.1	0.15	0.225	180	3000