MC100EP35: ECL JK Flip-Flop
The MC10EP35 is a higher speed/low voltage version of the EL35 JK flip flop. The JK data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.The 100 Series contains temperature compensation.
Features- 410 ps Propagation Delay
- Maximum Frequency > 3 GHz Typical
- PECL Mode Operatio Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -3.0V to -5.5V
- Open Input Default State
- Q Output will default LOW with inputs open or at VEE
- Pb-Free Packages are Available
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Applications- Using ECL Logic technologies for reducing system clock skew over the alternative CMOS and TTL technologies.
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Application Notes (16)
Data Sheets (1)
Simulation Models (1)
Package Drawings (3)
Order Information
| Product | Status | Compliance | Package | MSL* | Container | Budgetary Price/Unit |
|---|
| MC100EP35DG | Active | Pb-free
Halide free | SOIC-8 | 751-07 | 1 | Tube | 98 | Contact BDTIC |
| MC100EP35DR2G | Lifetime | Pb-free
Halide free | SOIC-8 | 751-07 | 1 | Tape and Reel | 2500 | |
| MC100EP35DTG | Active | Pb-free
Halide free | TSSOP-8 | 948R-02 | 3 | Tube | 100 | Contact BDTIC |
| MC100EP35DTR2G | Active | Pb-free
Halide free | TSSOP-8 | 948R-02 | 3 | Tape and Reel | 2500 | Contact BDTIC |
| MC100EP35MNR4G | Lifetime | Pb-free
Halide free | DFN-8 | 506AA | 1 | Tape and Reel | 1000 | |
Specifications
| Product | Type | Bits | Input Level | Output Level | VCC Typ (V) | tJitter Typ (ps) | tpd Typ (ns) | tsu Min (ns) | th Min (ns) | trec Typ (ns) | tR & tF Max (ps) | fToggle Typ (MHz) |
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| MC100EP35DG | JK-Type | 1 | ECL
CML | ECL | 3.3
5 | 0.2 | 0.41 | 0.15 | 0.15 | 0.15 | 170 | 3000 |
| MC100EP35DTG | JK-Type | 1 | CML
ECL | ECL | 5
3.3 | 0.2 | 0.41 | 0.15 | 0.15 | 0.15 | 170 | 3000 |
| MC100EP35DTR2G | JK-Type | 1 | ECL
CML | ECL | 5
3.3 | 0.2 | 0.41 | 0.15 | 0.15 | 0.15 | 170 | 3000 |
