MC100EP445: Serial to Parallel Converter, 3.3 V / 5 V, 8-bit ECL

The MC10/100EP445 is an integrated 8-bit differential serial to parallel data converter with frame asynchronous data resynchronization. The device is designed to operate for NRZ data rates of up to 5.0 Gb/s. The conversion sequence was chosen to convert the first serial bit to Q0, the second bit to Q1, etc. Two selectable differential serial inputs, which are selected by SINSEL, provide this device with loop-back testing capability. The MC10/100EP445 has a Sync pin which, when held high for at least two consecutive clock cycles, will swallow one bit of data shifting the start of the conversion data from Dn to Dn+1. Each additional shift requires an additional pulse to be applied to the Sync pin. Extra control pins are provided to reset and disable internal clock circuitry. Additionally, VBB pin is provided for single-ended input condition.The 100 Series contains temperature compensation.

Features
  • 1530 ps Propagation Delay
  • 5.0 Gb/s Data Rate Capability
  • Differential Clock and Serial Inputs
  • VBB Output for Single-Ended Input Applications
  • Asynchronous Data Synchronization (SYNC)
  • Asynchronous Master Reset (RESET)
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE =-3.0 V to -5.5 V
  • Open Input Default State
  • CLK ENABLE Immune to Runt Pulse Generation
  • Pb-Free Packages are Available
Applications
  • Serial to Parallel Converision
Application Notes (13)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
Serial / Parallel Converter, 3.3 V / 5 V, 8-bit ECLMC10EP445/D (145kB)16
Simulation Models (3)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for mc100ep445fa -3.3VMC100EP445FA_-33.IBS (6.0kB)1
IBIS Model for mc100ep445fa 3.3VMC100EP445FA_33.IBS (6.0kB)1
mc100ep445mn at 3.3 VMC100EP445MN_33.IBS (6.0kB)1
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN32, 5x5, 0.5P, 3.1x3.1EP488AM (57.4kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EP445FAGActivePb-free Halide freeLQFP-32Contact BDTIC2Tray JEDEC250Contact BDTIC
MC100EP445FAR2GLifetimePb-free Halide freeLQFP-32Contact BDTIC2Tape and Reel2000
MC100EP445MNGActivePb-free Halide freeQFN-32488AM1Tube74Contact BDTIC
MC100EP445MNR4GLifetimePb-free Halide freeQFN-32488AM1Tape and Reel1000
Specifications
ProductTypeBitsInput LevelOutput LevelVCC Typ (V)fdr Typ (Gb/sec)tpd Typ (ns)tsu Min (ns)th Min (ns)tJitter Typ (ps)tR & tF Max (ps)
MC100EP445FAGSerial/Parallel8CML ECLECL3.3 52.51.3-0.40.60.2400
MC100EP445MNGSerial/Parallel8ECL CMLECL3.3 52.51.3-0.40.60.2400
Serial / Parallel Converter, 3.3 V / 5 V, 8-bit ECL (145kB) MC10EP445
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for mc100ep445fa -3.3V MC100EP445
IBIS Model for mc100ep445fa 3.3V MC100EP445
mc100ep445mn at 3.3 V MC100EP445
QFN32, 5x5, 0.5P, 3.1x3.1EP NCN6804
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