MC100EP52: ECL Differential Clock/Data D Flip-Flop _ BDTIC a Leading Distributor in China

MC100EP52: ECL Differential Clock/Data D Flip-Flop

The MC10EP/100EP52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to VEE ) the outputs of the device will remain stable.

Features

330ps Typical Propagation Delay
Maximum Frequency > 4 GHz Typical
PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output will default LOW with inputs open or at VEE
Pb-Free Packages are Available

Applications

Negative edge-triggering

Application Notes (16)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

Package Drawings (3)

Document Title	Document ID/Size	Revision
DFN8 2.0x2.0x0.9mm, 0.5p	506AA (31.8kB)	F
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

Simulation Models (4)

Document Title	Document ID/Size	Revision
IBIS Model for MC100EP52D 3.3V	MC100EP52D_33.IBS (5.0kB)	1
IBIS Model for MC100EP52D at 0.0 V VCC and -5.2 V VEE	MC100EP52D_-52.IBS (6.0kB)	1
IBIS Model for MC100EP52DT with VEE at -5.2 V	MC100EP52DT_-52.IBS (6.0kB)	1
IBIS Model for mc10ep52dt 3.3V	MC10EP52DT_33.IBS (5.0kB)	1

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3 V / 5 V ECL Differential Data and Clock D Flip Flop	MC10EP52/D (183kB)	8	Aug, 2016

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
MC100EP52DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	Contact BDTIC
MC100EP52DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	Contact BDTIC
MC100EP52DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	Contact BDTIC
MC100EP52DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	Contact BDTIC
MC100EP52MNR4G	Active	Pb-free Halide free	DFN-8	506AA	1	Tape and Reel	1000	Contact BDTIC

Specifications

Product	Type	Bits	Input Level	Output Level	VCC Typ (V)	tJitter Typ (ps)	tpd Typ (ns)	tsu Min (ns)	tR & tF Max (ps)	fToggle Typ (MHz)
MC100EP52DG	D-Type	1	CML ECL	ECL	5 3.3	0.2	0.33	0.05	170	4000
MC100EP52DR2G	D-Type	1	CML ECL	ECL	5 3.3	0.2	0.33	0.05	170	4000
MC100EP52DTG	D-Type	1	ECL CML	ECL	3.3 5	0.2	0.33	0.05	170	4000
MC100EP52DTR2G	D-Type	1	ECL CML	ECL	5 3.3	0.2	0.33	0.05	170	4000
MC100EP52MNR4G	D-Type	1	CML ECL	ECL	5 3.3	0.2	0.33	0.05	170	4000