MC100EP56: Multiplexer, 2:1 Differential, Dual ECL, 3.3 V / 5.0 V

The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBB should be left open.The device features both individual and common select inputs to address both data path and random logic applications.The 100 Series contains temperature compensation.

Features
  • 360ps Typical Propagation Delays
  • Maximum Frequency > 3 GHz Typical
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Separate and Common Select
  • Q Output will default LOW with inputs open or at VEE
  • VBB Outputs
  • Pb-Free Packages are Available
Applications
  • Ideal for multiplexing low skew clock or other skew sensitive signals
Application Notes (16)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V / 5V ECL Dual Differential 2:1 MultiplexerMC10EP56/D (121kB)17
Simulation Models (3)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100EP56DT -3.3VMC100EP56DT_-33.IBS (11.0kB)3
IBIS Model for MC100EP56DT 3.3VMC100EP56DT_33.IBS (11.0kB)4
IBIS Model for MC100EP56DW 3.3VMC100EP56DW_33.IBS (11.0kB)3
Package Drawings (3)
Document TitleDocument ID/SizeRevision
QFN20, 4x4, 0.5P485E-01 (60.9kB)B
SOIC-20 WB751D-05 (36.3kB)H
TSSOP-20 WB948E-02 (39.7kB)D
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EP56DTGActivePb-free Halide freeTSSOP-20948E-021Tube75Contact BDTIC
MC100EP56DTR2GActivePb-free Halide freeTSSOP-20948E-021Tape and Reel2500Contact BDTIC
MC100EP56DWGActivePb-free Halide freeSOIC-20W751D-053Tube38Contact BDTIC
MC100EP56DWR2GActivePb-free Halide freeSOIC-20W751D-053Tape and Reel1000Contact BDTIC
MC100EP56MNGActivePb-free Halide freeQFN-20485E-011Tube92Contact BDTIC
MC100EP56MNTXGLast ShipmentsPb-free Halide freeQFN-20485E-011Tape and Reel3000
Specifications
ProductInput/Output RatioChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tJitter Typ (ps)tskew(OO) Max (ps)tpd Typ (ns)
MC100EP56DTG2:12CML ECLECL3.3 530000.21000.36
MC100EP56DTR2G2:12ECL CMLECL3.3 530000.21000.36
MC100EP56DWG2:12CML ECLECL3.3 530000.21000.36
MC100EP56DWR2G2:12ECL CMLECL3.3 530000.21000.36
MC100EP56MNG2:12ECL CMLECL3.3 530000.21000.36
3.3V / 5V ECL Dual Differential 2:1 Multiplexer (121kB) MC10EP56
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100EP56DT -3.3V MC100EP56
IBIS Model for MC100EP56DT 3.3V MC100EP56
IBIS Model for MC100EP56DW 3.3V MC100EP56
TSSOP-20 WB NLSX3018
SOIC-20 WB NLSX3018
QFN20, 4x4, 0.5P MC10EP57