MC100H646: PECL/TTL-TTL 1:8 Distribution Chip

The MC10H/100H646 is a single supply, low skew translating 1:8 clock driver. Devices in the H600 translator series utilize the 28-lead PLCC for optimal power pinning, signal flow through and electrical performance. The single supply H646 is similar to the H643, which is a dual supply 1:8 version of the same function. The H646 was designed specifically to drive series terminated transmission lines. Special techniques were used to match the HIGH and LOW output impedances to about 7ohms. This simplifies the choice of the termination resistor for series terminated applications. To match the HIGH and LOW output impedances, it was necessary to remove the standard IOS limiting resistor. As a result, the user should take care in preventing an output short to ground as the part will be permanently damaged. The H646 device meets all of the requirements for driving the 60 and 66MHz Pentium Microprocessor components, which greatly simplifies its implementation into a digital design. The eight copies of the clock allows for point-to-point clock distribution to simplify board layout and optimize signal integrity. The H646 provides differential PECL inputs for picking up LOW skew PECL clocks from the backplane and distributing it to TTL loads on a daughter board. When used in conjunction with the MC10/100E11 designed. In addition, a TTL level clock input is provided for flexibility. Note that only one of the inputs can be used on a single chip. For correct operation, the unused input pins should be left open. The Output Enable pin forces the outputs into a high impedance state when a logic 0 is applied. The output buffers of the H646 can drive two series terminated, 50 transmission lines each. This capability allows the to drive up to 16 different point-to-point clock loads. Refer to the Applications section for a more detailed discussion in this area. The 10H version is compatible with MECL 10H ECL logic levels. The 100H

Features
  • PECL/TTL-TTL Version of Popular ECLinPS E111
  • Low Skew
  • Guaranteed Skew Spec
  • Tri-State Enable
  • Differential Internal Design
  • VBB Output
  • Single Supply
  • Extra TTL and ECL Power/Ground Pins
  • Matched High and Low Output Impedance
  • Meets Specifications Required to Drive the Pentium Microprocessor
  • Pb-Free Packages are Available
Application Notes (14)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
PECL/TTL-TTL 1:8 Distribution ChipMC10H646/D (128.0kB)5
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100H646FN - Positive ECLMC100H646FN_PECL.IBS (10.0kB)0
Package Drawings (1)
Document TitleDocument ID/SizeRevision
28 LEAD PLCC776-02 (67.7kB)F
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100H646FNGActivePb-free Halide freePLCC-28776-023Tube37Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100H646FNGBuffer12:1:8ECLTTL5350 5005.35 4.9150080
PECL/TTL-TTL 1:8 Distribution Chip (128.0kB) MC100H646
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for MC100H646FN - Positive ECL MC100H646
28 LEAD PLCC MC10H604