MC100H680: 4-Bit Differential ECL Bus/TTL Bus Transceiver

The MC10H/100H680 is a dual supply 4-bit differential ECL bus to TTL bus transceiver. It is designed to allow the system designer to no longer be limited in bus speed associated with standard TTL busses. Using a differential ECL Bus will increase the frequency of operation and increase noise immunity. Both the TTL and the ECL ports are capable of driving a bus. The ECL outputs have the ability to drive 25 ?, allowing both ends of the bus line to be terminated in the characteristic impedance of 50 ?. The TTL outputs are specified to source 15mA and sink 48 mA, allowing the ability to drive highly capacitive loads. The ECL output levels are VOH approximately equal to -1.0V and VOL cutoff equal to -2.0 V (VTT). When the ECL ports are disabled both EIOx and EIOxB go to the VOL cutoff level. The ECL input receivers have special circuitry which detects this disabled condition, prevents oscillation, and forces the TTL output to the low state. The noise margin in this disabled state is greater than 600 mV. Multiple ECL VCCO pins are utilized to minimize switching noise. The TTL ports have standard levels. The TTL input receivers have PNP input devices to significantly reduce loading. Multiple TTL power and ground pins are utilized to minimize switching noise. The control pins (EDIR and ECEB) of the 10H version is compatible with MECL 10H ECL logic levels. The control pins of the 100H version are compatible with 100K levels.

Features
  • Differential ECL Bus (25 W) I/O Ports PIN DESCRIPTIONS
  • High Drive TTL Bus I/O Ports Pin Symbol
  • Extra TTL and ECL Power/Ground Pins to Minimize 1 GT1 Switching Noise 2 TIO0
  • Dual Supply 3 TDIR
  • Direction and Chip Enable Control Pins 4 EDIR 5 EIO0 6 VCCO1
  • Pb-Free Packages are Available
Application Notes (10)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Package Drawings (1)
Document TitleDocument ID/SizeRevision
28 LEAD PLCC776-02 (67.7kB)F
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
4-Bit Differential ECL Bus/TTL Bus TransceiverMC10H680/D (137.0kB)10
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100H680FNGActivePb-free Halide freePLCC-28776-023Tube37Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100H680FNGSignal Driver41:1ECLTTL53.23400
4-Bit Differential ECL Bus/TTL Bus Transceiver (137.0kB) MC100H680
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
28 LEAD PLCC MC10H604