MC100LVEL05: ECL 2-Input Differential AND/NAND Gate _ BDTIC a Leading Distributor in China

MC100LVEL05: ECL 2-Input Differential AND/NAND Gate

The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3V supply voltage. With propagation delays and output transition times equivalent to the EL05, the LVEL05 is ideally suited for those applications which require the ultimate in AC performance at low voltage power supplies. Because a negative 2-input NAND is equivalent to a 2-input OR function, the differential inputs and outputs of the device allows the LVEL05 to also be used as a 2-input differential OR/NOR gate.

Features

340ps Propagation Delay
High Bandwidth Output Transitions
ESD Protection: >4 KV HBM, >200 V MM
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V
NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with All Inputs Open or at VEE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 69 devices
Pb-Free Packages are Available

Application Notes (15)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3 V ECL 2-Input Differential AND/NAND	MC100LVEL05/D (163kB)	5	Jul, 2016

Simulation Models (3)

Document Title	Document ID/Size	Revision
IBIS Model for mc100lvel05d	MC100LVEL05D_33.IBS (5.0kB)	2
IBIS Model for mc100lvel05dt	MC100LVEL05DT_33.IBS (5.0kB)	1
Low Voltage ECLinPS SPICE Modeling Kit	AN1560/D (88.0kB)	5

Package Drawings (2)

Document Title	Document ID/Size	Revision
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
MC100LVEL05DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	Contact BDTIC
MC100LVEL05DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	Contact BDTIC
MC100LVEL05DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	Contact BDTIC
MC100LVEL05DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	Contact BDTIC

Specifications

Product	Type	Channels	Input Level	Output Level	VCC Typ (V)	fToggle Max (MHz)	tpd Typ (ns)	tJitter Typ (ps)	tR & tF Max (ps)
MC100LVEL05DG	AND/NAND	1	LVDS ECL	ECL	3.3	2000	0.34	1	320
MC100LVEL05DR2G	AND/NAND	1	LVDS ECL	ECL	3.3	2000	0.34	1	320
MC100LVEL05DTG	AND/NAND	1	LVDS ECL	ECL	3.3	2000	0.34	1	320
MC100LVEL05DTR2G	AND/NAND	1	LVDS ECL	ECL	3.3	2000	0.34	1	320