MC100LVEL37: Clock / Data Fanout Buffer, 1:4 Differential, ÷1 / ÷2, 3.3 V

The MC100LVEL37 is a fully differential 1:4 fanout buffer. The device offers two outputs at 1 of the input frequency, and two outputs at 2 of the input frequency. The Low Output-Output Skew of the device makes it ideal for distributing 1x and 1/2x frequency synchronous signals. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the CLKn input will pull down to VEE. The CLKnbar input will bias around VCC/2 and the Qn output will go LOW.

Features
  • 700ps Typical Propagation Delays
  • 50 ps Maximum Output-Output Skews
  • ESD Protection: >2 KV HBM, >200 V MM
  • The 100 Series Contains Temperature Compensation
  • PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V
  • Internal Input Pulldown Resistors
  • Qn Output will Default LOW with Inputs Open or at VEE
  • Qn Output will Default LOW with Inputs Open or at VEE
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 256 devices
  • Pb-Free Packages are Available
Application Notes (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V ECL 1:4 ÷1 / ÷2 Clock Fanout BufferMC100LVEL37/D (146kB)7Jul, 2016
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for mc100lvel37dw 3.3VMC100LVEL37DW_33.IBS (10.0kB)2
Low Voltage ECLinPS SPICE Modeling KitAN1560/D (88.0kB)5
Package Drawings (1)
Document TitleDocument ID/SizeRevision
SOIC-20 WB751D-05 (36.3kB)H
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100LVEL37DWGActivePb-free Halide freeSOIC-20W751D-053Tube38Contact BDTIC
MC100LVEL37DWR2GActivePb-free Halide freeSOIC-20W751D-053Tape and Reel1000Contact BDTIC
Specifications
ProductTypeInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100LVEL37DWGDividerECL LVDSECL3.310000.7550
MC100LVEL37DWR2GDividerECL LVDSECL3.310000.7550
3.3 V ECL 1:4 ÷1 / ÷2 Clock Fanout Buffer (146kB) MC100LVEL37
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for mc100lvel37dw 3.3V MC100LVEL37
Low Voltage ECLinPS SPICE Modeling Kit MC100LVELT23
SOIC-20 WB NLSX3018
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