MC100LVEL40: Phase - Frequency Detector, Differential, ECL, 3.3 V / 5.0 V

The MC100LVEL40 is a three state phase frequency-detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate of the R and V inputs should be less than 5 ns. The device is designed to work with a 3.3 V power supply.When the reference (R) and the feedback (FB) inputs are unequal in frequency and/or phase the differential up (U) and down (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.For application information, see AND8040/D, "Phase Lock Loop Operation."The 100 Series Contains Temperature Compensation

Features
  • 250MHz Typical Bandwidth
  • ESD Protection: >2 KV HBM
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Internal Input Pulldown Resistors
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 356 devices
  • Pb-Free Packages are Available
Application Notes (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3/5V ECL Differential Phase-Frequency DetectorMC100LVEL40/D (114.0kB)8
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
Low Voltage ECLinPS SPICE Modeling KitAN1560/D (88.0kB)5
Package Drawings (1)
Document TitleDocument ID/SizeRevision
SOIC-20 WB751D-05 (36.3kB)H
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100LVEL40DWGActivePb-free Halide freeSOIC-20W751D-053Tube38Contact BDTIC
MC100LVEL40DWR2GActivePb-free Halide freeSOIC-20W751D-053Tape and Reel1000Contact BDTIC
Specifications
ProductInput LevelOutput LevelVCC Typ (V)Transfer Gain Typ (mV/degree)CMRR Max (V)fToggle Max (MHz)tpd Typ (ns)tJitter Typ (ps)tR & tF Max (ps)
MC100LVEL40DWGECL LVDS CMLECL3.3 521.22501.350.2475
MC100LVEL40DWR2GECL LVDS CMLECL3.3 521.22501.350.2475
3.3/5V ECL Differential Phase-Frequency Detector (114.0kB) MC100LVEL40
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
Low Voltage ECLinPS SPICE Modeling Kit MC100LVELT23
SOIC-20 WB NLSX3018