MC100LVEP11: ECL 1:2 Differential Clock / Data Fanout Buffer

The MC10LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for applications requiring lower voltage. Single ended CLK input operation is limited to a VCC >= 3.0 V in PECL mode, or VEE <= -3.0 V in NECL mode.The 100 Series contains temperature compensation.

Features

240 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC= 2.375 V to 3.8 V with VEE= 0 V
NECL Mode Operating Range: VCC= 0 V with VEE= -2.375 V to -3.8 V
Open Input Default State
Q Outputs will default LOW with inputs open or at VEE
LVDS Input Compatible

Applications

GbE or Fibre Channel Redundant Fan-out

Application Notes (16)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
2.5 V / 3.3 V ECL 1:2 Differential Fanout Buffer	MC10LVEP11/D (243kB)	14	Aug, 2016

Simulation Models (3)

Document Title	Document ID/Size	Revision
IBIS Model for MC100LVEP11D at 3.3V	MC100LVEP11D_33V.IBS (5.0kB)	2
IBIS Model for mc100lvep11dt 2.5V	MC100LVEP11DT_25.IBS (5.0kB)	3
IBIS Model for mc100lvep11dt 3.3V	MC100LVEP11DT_33.IBS (6.0kB)	2

Package Drawings (3)

Document Title	Document ID/Size	Revision
DFN8 2.0x2.0x0.9mm, 0.5p	506AA (31.8kB)	F
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
MC100LVEP11DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	Contact BDTIC
MC100LVEP11DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	Contact BDTIC
MC100LVEP11DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	Contact BDTIC
MC100LVEP11DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	Contact BDTIC
MC100LVEP11MNR4G	Active	Pb-free Halide free	DFN-8	506AA	1	Tape and Reel	1000	Contact BDTIC

Specifications

Product	Type	Channels	Input / Output Ratio	Input Level	Output Level	VCC Typ (V)	tJitterRMS Typ (ps)	tskew(o-o) Max (ps)	tpd Typ (ns)	tR & tF Max (ps)	fmaxClock Typ (MHz)
MC100LVEP11DG	Buffer	1	1:2	CML LVDS ECL	ECL	3.3 2.5	1.42	20	0.24	170	3000
MC100LVEP11DR2G	Buffer	1	1:2	LVDS ECL CML	ECL	2.5 3.3	1.42	20	0.24	170	3000
MC100LVEP11DTG	Buffer	1	1:2	CML ECL LVDS	ECL	3.3 2.5	1.42	20	0.24	170	3000
MC100LVEP11DTR2G	Buffer	1	1:2	ECL CML LVDS	ECL	3.3 2.5	1.42	20	0.24	170	3000
MC100LVEP11MNR4G	Buffer	1	1:2	LVDS ECL CML	ECL	2.5 3.3	1.42	20	0.24	170	3000