MC100LVEP14: 2.5 V / 3.3 V 1:5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer

The MC100LVEP14 is a low skew 1 to 5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions.

Features
  • 100 ps Device-to-Device Skew
  • 25 ps Within Device Skew
  • 400 ps Typical Propagation Delay
  • Maximum Frequency > 2 GHz Typical
  • PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V
  • NECL Mode: VCC = 0 V with VEE = -2.375 V to -3.8 V
  • LVDS Input Compatible
  • Open Input Default State
Application Notes (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock DriverMC100LVEP14/D (90kB)14
Simulation Models (3)
Document TitleDocument ID/SizeRevisionRevision Date
ECLinPS Plus SPICE Modeling KitAND8009 (343.0kB)11
IBIS Model for MC100LVEP14DT 2.5VMC100LVEP14DT_25.IBS (9.0kB)3
IBIS Model for MC100LVEP14DT 3.3VMC100LVEP14DT_33.IBS (10.0kB)2
Package Drawings (1)
Document TitleDocument ID/SizeRevision
TSSOP-20 WB948E-02 (39.7kB)D
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100LVEP14DTGActivePb-free Halide freeTSSOP-20948E-021Tube75Contact BDTIC
MC100LVEP14DTR2GActivePb-free Halide freeTSSOP-20948E-021Tape and Reel2500Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100LVEP14DTGBuffer12:1:5HSTL CML ECL LVDSECL2.5 3.30.181250.42252000
MC100LVEP14DTR2GBuffer12:1:5LVDS HSTL CML ECLECL3.3 2.50.181250.42252000
2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver (90kB) MC100LVEP14
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
ECLinPS Plus SPICE Modeling Kit NB4N840M
IBIS Model for MC100LVEP14DT 2.5V MC100LVEP14
IBIS Model for MC100LVEP14DT 3.3V MC100LVEP14
TSSOP-20 WB NLSX3018
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