MC100LVEP210: Clock Driver, 1:5 Differential, Dual ECL / PECL / HSTL, 2.5 V / 3.3 V

The MC100LVEP210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be used when the EP210 is operating in PECL mode.The LVEP210 specifically guarantees low output-to-output skew.Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 ohms even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.The MC100LVEP210, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVEP210 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. Single-ended CLK input operation is limited to a VCC ≤ 3.0 V in PECL mode, or VEE ≤ -3.0 V in ECL mode.Designers can take advantage of the LVEP210's performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D.

Features
  • 85 ps Typical Device-to-Device Skew
  • 20 ps Typical Output-to-Output Skew
  • VBBOutput
  • Jitter Less than 1 ps RMS
  • 350 ps Typical Propagation Delay
  • Maximum Frequency >3 Ghz
  • The 100 Series Contains Temperature Compensation
  • PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V
  • Open Input Default State
  • LVDS Input Compatible
Application Notes (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN32, 5x5, 0.5P, 3.1x3.1EP488AM (57.4kB)A
Simulation Models (4)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100LVEP210FA -2.5VEEMC100LVEP210FA_-25.IBS (14.0kB)4
IBIS Model for MC100LVEP210FA -3.3VEEMC100LVEP210FA_-33.IBS (15.0kB)4
IBIS Model for MC100LVEP210FA 2.5VMC100LVEP210FA_25.IBS (14.0kB)4
IBIS Model for MC100LVEP210FA 3.3VMC100LVEP210FA_33.IBS (15.0kB)4
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock DriverMC100LVEP210/D (103kB)15
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100LVEP210FAGActivePb-free Halide freeLQFP-32Contact BDTIC2Tray JEDEC250Contact BDTIC
MC100LVEP210FARGActivePb-free Halide freeLQFP-32Contact BDTIC2Tape and Reel2000Contact BDTIC
MC100LVEP210MNGLast ShipmentsPb-free Halide freeQFN-32488AM1Tube74
MC100LVEP210MNRGActivePb-free Halide freeQFN-32488AM1Tape and Reel2500Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100LVEP210FAGBuffer21:5HSTL LVDS ECL CMLECL3.3 2.50.207250.352503000
MC100LVEP210FARGBuffer21:5CML HSTL LVDS ECLECL3.3 2.50.207250.352503000
MC100LVEP210MNRGBuffer21:5CML HSTL LVDS ECLECL3.3 2.50.207250.352503000
2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver (103kB) MC100LVEP210
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100LVEP210FA -2.5VEE MC100LVEP210
IBIS Model for MC100LVEP210FA -3.3VEE MC100LVEP210
IBIS Model for MC100LVEP210FA 2.5V MC100LVEP210
IBIS Model for MC100LVEP210FA 3.3V MC100LVEP210
QFN32, 5x5, 0.5P, 3.1x3.1EP NCN6804