MC10E416: Quint Differential Line Receiver

The MC10E416/100E416 is a 5-bit differential line receiving device. The 2.0 GHz of bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. The differential inputs have internal clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state. Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device. Note that the input clamp will take affect only if both inputs fall 2.5 V below VCC . The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation.

Features
  • Differential D and Q; VBB available
  • 600ps Max. Propagation Delay
  • High Frequency Outputs
  • 2 Stages of Gain
  • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors
  • ESD Protection: > 2 kV HBM, > 200 V MM
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 201 devices
  • Pb-Free Packages are Available
Application Notes (17)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS and ECLinPS Lite SPICE I/O Modeling KitAN1503/D (120.0kB)6
ECLinPS™ Circuit Performance at Non-Standard VIH LevelsAN1404/D (51.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Package Drawings (1)
Document TitleDocument ID/SizeRevision
28 LEAD PLCC776-02 (67.7kB)F
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
5V ECL Quint Differential Line ReceiverMC10E416/D (132.0kB)7
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC10E416FNR2GActivePb-free Halide freePLCC-28776-023Tape and Reel500Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC10E416FNR2GSignal Driver51:1ECLECL5<1100.353502000
5V ECL Quint Differential Line Receiver (132.0kB) MC10E416
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit MC100EP91
ECLinPS™ Circuit Performance at Non-Standard VIH Levels MC10E195
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
28 LEAD PLCC MC10H604