MC10EL32: 5.0 V ECL ÷·2 Divider _ BDTIC a Leading Distributor in China

MC10EL32: 5.0 V ECL ÷·2 Divider

The MC10EL/100EL32 is an integrateddivide by 2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01 F capacitor. Also note that the VBB is designed to be used as an input bias on the EL32 only, the VBB output has limited current sink and source capability. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the synchronization of multiple EL32's in a system.The 100 Series contains temperature compensation.

Features

510ps Propagation Delay
3.0GHz Toggle Frequency
ESD Protection: > 1 KV HBM, > 100 V MM
PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V
NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V
Internal Input Pulldown Resistors on CLK(s) and R.
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 82 devices

Applications

Phase Lock Loops

Application Notes (17)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit	AN1503/D (120.0kB)	6
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
5 V ECL Divide by 2 Divider	MC10EL32/D (165kB)	9	Jul, 2016

Simulation Models (2)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for mc10el32d -5.0V	MC10EL32D_-50.IBS (9.0kB)	1
IBIS Model for mc10el32d 5.0V	MC10EL32D_50.IBS (9.0kB)	1

Package Drawings (2)

Document Title	Document ID/Size	Revision
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
MC10EL32DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	Contact BDTIC
MC10EL32DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	Contact BDTIC
MC10EL32DTG	Last Shipments	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100
MC10EL32DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	Contact BDTIC