MC10EP016: ECL 8-Bit Synchronous Binary Counter

The MC10/100EP016 is a high-speed synchronous, presettable, cascadeable 8-bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family.The counter features internal feedback to TCbar gated by the TCLD (Terminal Count Load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the TCbar feedback is disabled, and counting proceeds continuously, with TCbar going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated.COUT and COUTbar provide differential outputs from a single, non-cascaded counter or divider application. COUT and COUTbar should not be used in cascade configuration. Only TCbar should be used for a counter or divider cascade chain output.A differential clock input has also been added to improve performance.The 100 Series contains temperature compensation.

Features
  • 500 ps Typical Propagation Delay
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Internal TCbar Feedback (Gated)
  • Addition of COUT and COUTbar
  • 8-Bit
  • Differential Clock Input
  • VBB Output
  • Fully Synchronous Counting and TCbar Generation
  • Asynchronous Master Reset
  • Pb-Free Packages are Available
Application Notes (16)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V / 5V ECL 8-Bit Synchronous Binary Up CounterMC10EP016/D (189.0kB)12
Simulation Models (3)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC10EP016FA -5.2 VEEMC10EP016FA_-52.IBS (8.0kB)2
IBIS Model for MC10EP016FA 3.3VMC10EP016FA_33.IBS (6.0kB)3
IBIS Model for MC10EP016FA for -3.3VMC10EP016FA_-33.IBS (8.0kB)3
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC10EP016FAGActivePb-free Halide freeLQFP-32Contact BDTIC2Tray JEDEC250Contact BDTIC
MC10EP016FAR2GActivePb-free Halide freeLQFP-32Contact BDTIC2Tape and Reel2000Contact BDTIC
Specifications
ProductTypeInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC10EP016FAGCounterCML ECLECL5 3.310000.5320
MC10EP016FAR2GCounterCML ECLECL5 3.310000.5320
3.3V / 5V ECL 8-Bit Synchronous Binary Up Counter (189.0kB) MC10EP016
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC10EP016FA -5.2 VEE MC10EP016
IBIS Model for MC10EP016FA 3.3V MC10EP016
IBIS Model for MC10EP016FA for -3.3V MC10EP016