MC10EP195: 3.3 V ECL Programmable Delay Chip

NECL/PECL input transition.The delay section consists of a programmable matrix of gates and multiplexers as shown in the data sheet logic diagram. The delay increment of the EP195 has a digitally selectable resolution of about 10 ps and a range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D(0:9) which are latched on chip by a high signal on the latch enable (LEN) control. The MC10/100EP195 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in the data sheet.Because the EP195 is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin D10 is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs. Select input pins D0-D10 may be threshold controlled by combinations of interconnects between VEF (pin 7) and VCF (pin 8) for CMOS, ECL, or TTL level signals. For CMOS input levels, leave VCF and VEF open. For ECL operation, short VCF and VEF (pins 7 and 8). For TTL level operation, connect a 1.5 V supply reference to VCF and leave open VEF pin. The 1.5 V reference voltage to VCF pin can be accomplished by placing a 1.5k Ohm or 500 Ohm resistor between VCF and VEE for 3.3 V or 5.0 V power supplies, respectively. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or

Features
  • Maximum Frequency > 1.2 Ghz Typical
  • Programmable Range: 2.2 ns to 12.2 ns
  • 10 ps Increments
  • PECL Mode Operating Range: VCC = 3.0 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • A Logic High on the ENbar Pin Will Force Q to Logic Low
  • D[0:10] Can Accept Either ECL, CMOS, or TTL Inputs.
  • VBB Output Reference Voltage
  • Pb-Free Packages are Available
Applications
  • Automated Test Equipement (ATE)
  • General Purpose Data and Clock Interface
Application Notes (14)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V ECL Programmable Delay ChipMC10EP195/D (150kB)19
Simulation Models (3)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC10EP195FA 3.3V_CMOSMC10EP195FA_33_CMOS.IBS (26.0kB)3
IBIS Model for MC10EP195FA 3.3V_ECLMC10EP195FA_33_ECL.IBS (26.0kB)3
IBIS Model for MC10EP195FA 3.3V_TTLMC10EP195FA_33_TTL.IBS (26.0kB)3
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN32, 5x5, 0.5P, 3.1x3.1EP488AM (57.4kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC10EP195FAGActivePb-free Halide freeLQFP-32Contact BDTIC2Tray JEDEC250Contact BDTIC
MC10EP195FAR2GLifetimePb-free Halide freeLQFP-32Contact BDTIC2Tape and Reel2000
MC10EP195MNGLifetimePb-free Halide freeQFN-32488AM1Tube74
MC10EP195MNR4GActivePb-free Halide freeQFN-32488AM1Tape and Reel1000Contact BDTIC
Specifications
ProductInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)td(prog) Min (ns)td(prog) Max (ns)td(step) Typ (ps)tJitter Typ (ps)tR & tF Max (ps)
MC10EP195FAGECL CMLECL3.312007.8510.95141.16 1.09200 135
MC10EP195MNR4GECL CMLECL3.312007.8510.95141.16 1.09200 135
3.3V ECL Programmable Delay Chip (150kB) MC10EP195
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC10EP195FA 3.3V_CMOS MC10EP195
IBIS Model for MC10EP195FA 3.3V_ECL MC10EP195
IBIS Model for MC10EP195FA 3.3V_TTL MC10EP195
QFN32, 5x5, 0.5P, 3.1x3.1EP NCN6804