MC10H123: Triple 4-3-3-Input Bus Driver

The MC10H123 is a triple 4-3-3-Input Bus Driver. The MC10H123 consists of three NOR gates designed for bus driving applications on card or between cards. Output low logic levels are specified with VOL = -2.1 Vdc so that the bus may be terminated to -2.0 Vdc. The gate output, when low, appears as a high impedance to the bus, because the output emitter-followers of the MC10H123 are "turned-off." This eliminates discontinuities in the characteristic impedance of the bus. The VOH level is specified when driving a 25-ohm load terminated to -2.0 Vdc, the equivalent of a 50-ohm bus terminated at both ends. Although 25 ohms is the lowest characteristic impedance that can be driven by the MC10H123, higher impedance values may be used with this part. A typical 50-ohm bus is shown in Figure 1.

Features
  • Propagation Delay, 1.5 ns Typical
  • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
  • Voltage Compensated
  • MECL 10K-Compatible
  • Pb-Free Packages are Available
Application Notes (10)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Package Drawings (2)
Document TitleDocument ID/SizeRevision
20 LEAD PLLC775-02 (60.9kB)F
PDIP-16648-08 (34.2kB)V
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
Triple 4-3-3-Input Bus DriverMC10H123/D (140kB)8Aug, 2016
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC10H123FNGActivePb-free Halide freePLLC-20775-023Tube46Contact BDTIC
MC10H123FNR2GActivePb-free Halide freePLLC-20775-023Tape and Reel500Contact BDTIC
MC10H123PGLast ShipmentsPb-free Halide freePDIP-16648-08NATube25
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC10H123FNGSignal Driver34:1ECLECL-5.21.151600
MC10H123FNR2GSignal Driver34:1ECLECL-5.21.151600
Triple 4-3-3-Input Bus Driver (140kB) MC10H123
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
20 LEAD PLLC MC10H351
PDIP-16 MC10H350