MC10H135: Dual Master-Slave JK Flip-Flop

The MC10H135 is a dual JK master-slave flip-flop. The device is provided with an asynchronous set(s) and reset(R). These set and reset inputs overide the clock. A common clock is provided with separate Jbar-Kbar inputs. When the clock is static, the JK bar inputs do not effect the output. The output states of the flip flop change on the positive transition of the clock.

Features
  • Propagation delay, 1.5 ns Typical
  • Power Dissipation, 280 mW mV Typical/Pkg. (No Load)
  • ftog 250 MHz Max
  • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
  • Voltage Compensated
  • MECL 10K Compatible
  • Pb-Free Packages are Available
Application Notes (10)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Package Drawings (2)
Document TitleDocument ID/SizeRevision
20 LEAD PLLC775-02 (60.9kB)F
PDIP-16648-08 (34.2kB)V
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
Dual J-K Master-Slave Flip-FlopMC10H135/D (135kB)9Aug, 2016
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC10H135FNGLast ShipmentsPb-free Halide freePLLC-20775-023Tube46
MC10H135FNR2GActivePb-free Halide freePLLC-20775-023Tape and Reel500Contact BDTIC
MC10H135PGLast ShipmentsPb-free Halide freePDIP-16648-08NATube25
Specifications
ProductTypeBitsInput LevelOutput LevelVCC Typ (V)tJitter Typ (ps)tpd Typ (ns)tsu Min (ns)th Min (ns)trec Typ (ns)tR & tF Max (ps)fToggle Typ (MHz)
MC10H135FNR2GJK-Type2ECLECL-5.21.651.512200250
Dual J-K Master-Slave Flip-Flop (135kB) MC10H135
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
20 LEAD PLLC MC10H351
PDIP-16 MC10H350