MC10H601: 9-Bit ECL-TTL Translator

The MC10H/100H601 is a 9-bit, dual supply ECL to TTL translator. Devices in the 9-bit translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The devices feature a 48 mA TTL output stage, and AC performance is specified into both a 50 pF and 200 pF load capacitance. For the 3-state output disable, both ECL and TTL control inputs are provided, allowing maximum design flexibility. The 10H version is compatible with MECL 10H ECL logic levels. The 100H version is compatible with 100K levels.

Features
  • 9-Bit Ideal for Byte-Parity Applications
  • 3-State TTL Outputs
  • Flow-Through Configuration
  • Extra TTL and ECL Power Pins to Minimize Switching Noise
  • ECL and TTL 3-State Control Inputs
  • Dual Supply
  • 4.8 ns Max Delay into 50 pF, 9.6 ns into 200 pF (all outputs switching)
  • PNP TTL Inputs for Low Loading Figure 2. Logic Diagram 10/97 W Motorola, Inc. 1997 2-1
  • Pb-Free Packages are Available
Application Notes (13)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing with ECLinPSAND8066/D (72kB)3
MC10/100H60x Translator Family I/O SPICE Modelling KitAN1402/D (159.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Package Drawings (1)
Document TitleDocument ID/SizeRevision
28 LEAD PLCC776-02 (67.7kB)F
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
9-Bit ECL/TTL TranslatorMC10H601/D (110.0kB)12
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC10H601FNGActivePb-free Halide freePLCC-28776-023Tube37Contact BDTIC
MC10H601FNR2GActivePb-free Halide freePLCC-28776-023Tape and Reel500Contact BDTIC
Specifications
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC10H601FNG1ECLTTL53.251200 3000
MC10H601FNR2G1ECLTTL53.253000 1200
9-Bit ECL/TTL Translator (110.0kB) MC10H601
AC Characteristics of ECL Devices NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing with ECLinPS NB100LVEP91
MC10/100H60x Translator Family I/O SPICE Modelling Kit MC10H604
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
28 LEAD PLCC MC10H604