MC10H640: ECL/TTL Clock Driver

The MC10H/100H640 generates the necessary clocks for the 68030, 68040 and similar microprocessors. It is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of part-to-part skew, within-part skew and also duty cycle skew. The user has a choice of using either TTL or PECL (ECL referenced to +5.0V) for the input clock. TTL clocks are typically used in present MPU systems. However, as clock speeds increase to 50MHz and beyond, the inherent superiority of ECL (particularly differential ECL) as a means of clock signal distribution becomes increasingly evident. The H640 also uses differential PECL internally to achieve its superior skew characteristic. The H640 includes divide-by-two and divide-by-four stages, both to achieve the necessary duty cycle skew and to generate MPU clocks as required. A typical 50MHz processor application would use an input clock running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz (see Logic Symbol). The 10H version is compatible with MECL 10H ECL logic levels, while the 100H version is compatible with 100K levels (referenced to +5.0V).

Features
  • Generates Clocks for 68030/040
  • Meets 030/040 Skew Requirements
  • TTL or PECL Input Clock
  • Extra TTL and PECL Power/Ground Pins
  • Asynchronous Reset
  • Single +5.0V Supply Function Reset (R): LOW on RESET forces all Q outputs LOW and all Q outputs HIGH. Power-Up: The device is designed to have the POS edges of the �b8;2 and Select (SEL): LOW selects the ECL input source (DE/DE). HIGH selects the TTL input
  • Pb-Free Packages are Available
Application Notes (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
68030/040 PECL-TTL Clock DriverMC10H640/D (149kB)9Aug, 2016
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for mc10h640fnMC10H640FN.IBS (6.0kB)1
Package Drawings (1)
Document TitleDocument ID/SizeRevision
28 LEAD PLCC776-02 (67.7kB)F
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC10H640FNGActivePb-free Halide freePLCC-28776-023Tube37Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC10H640FNGBuffer12:6ECLTTL550052500135
68030/040 PECL-TTL Clock Driver (149kB) MC10H640
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for mc10h640fn MC10H640
28 LEAD PLCC MC10H604