MC74HC112A: Dual JK Flip-Flop with Set and Reset
High Performance Silicon Gate CMOS The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative edge clocked and has active low asynchronous Set and Reset inputs. The HC112A is identical in function to the HC76, but has a different pinout.
Features- Output Drive Capability: 10 LSTTL Loads
- Outputs Directly Interface to CMOS, NMOS, and TTL
- Operating Voltage Range: 2.0 to 6.0 V
- Low Input Current: 1.0 A
- High Noise Immunity Characteristic of CMOS Devices
- In Compliance with the Requirements Defined by JEDEC Standard No. 7A
- Similar in Function to the LS112 Except When Set and Reset are Low Simultaneously
- Chip Complexity: 100 FETs or 25 Equivalent Gates
- PbFree Packages are Available
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Applications- Desktop, White Goods, etc.
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Data Sheets (1)
Package Drawings (2)
Order Information
| Product | Status | Compliance | Package | MSL* | Container | Budgetary Price/Unit |
|---|
| MC74HC112ADG | Active | Pb-free
Halide free | SOIC-16 | 751B-05 | 1 | Tube | 48 | $0.104 |
| MC74HC112ADR2G | Active | Pb-free
Halide free | SOIC-16 | 751B-05 | 1 | Tape and Reel | 2500 | $0.104 |
| MC74HC112ADTG | Active | Pb-free
Halide free | TSSOP-16 | 948F-01 | 1 | Tube | 96 | $0.104 |
| MC74HC112ADTR2G | Active | Pb-free
Halide free | TSSOP-16 | 948F-01 | 1 | Tape and Reel | 2500 | $0.104 |
Specifications
| Product | Type | Channels | VCC Min (V) | VCC Max (V) | tpd Max (ns) | IO Max (mA) |
|---|
| MC74HC112ADG | JK-Type | 2 | 2 | 6 | 21 | 5.2 |
| MC74HC112ADR2G | JK-Type | 2 | 2 | 6 | 21 | 5.2 |
| MC74HC112ADTG | JK-Type | 2 | 2 | 6 | 21 | 5.2 |
| MC74HC112ADTR2G | JK-Type | 2 | 2 | 6 | 21 | 5.2 |
