MC74HC4046A: Phase Locked Loop

High-Performance Silicon-Gate CMOS The MC74HC4046A is similar in function to the MC14046 Metal gate CMOS device. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC4046A phase-locked loop contains three phase comparators, a voltage-controlled oscillator (VCO) and unity gain op-amp DEMOUT. The comparators have two common signal inputs, COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self-bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1OUT and maintains 90 degrees phase shift at the center frequency between SIGIN and COMPIN signals (both at 50% duty cycle). Phase comparator 2 (with leading-edge sensing logic) provides digital error signals PC2OUT and PCPOUT and maintains a 0 degree phase shift between SIGIN and COMPIN signals (duty cycle is immaterial). The linear VCO produces an output signal VCOOUT whose frequency is determined by the voltage of input VCOIN signal and the capacitor and resistors connected to pins C1A, C1B, R1 and R2. The unity gain op-amp output DEMOUT with an external resistor is used where the VCOIN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all op-amps to minimize standby power consumption. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency conversion and motor speed control.

Features
  • Output Drive Capability: 10 LSTTL Loads
  • Low Power Consumption Characteristic of CMOS Devices
  • Operating Speeds Similar to LSTTL
  • Wide Operating Voltage Range: 3.0 to 6.0 V
  • Low Input Current: 1.0 mA Maximum (except SIGIN and COMPIN)
  • In Compliance with the Requirements Defined by JEDEC Standard No. 7A
  • Low Quiescent Current: 80 mA Maximum (VCO disabled)
  • High Noise Immunity Characteristic of CMOS Devices
  • Diode Protection on all Inputs
  • Chip Complexity: 279 FETs or 70 Equivalent Gates
  • Pb-Free Packages are Available*
Application Notes (1)
Document TitleDocument ID/SizeRevisionRevision Date
Configuring and Applying the MC74HC4046A Phase-Locked LoopAN1410/D (102.0kB)3
Package Drawings (2)
Document TitleDocument ID/SizeRevision
SOIC 16 LEAD751B-05 (38.2kB)K
TSSOP-16948F-01 (41.7kB)B
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
Phase-Locked LoopMC74HC4046A/D (169kB)11Aug, 2014
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC74HC4046ADGActivePb-free Halide freeSOIC-16751B-051Tube48Contact BDTIC
MC74HC4046ADR2GActivePb-free Halide freeSOIC-16751B-051Tape and Reel2500Contact BDTIC
MC74HC4046ADTGActivePb-free Halide freeTSSOP-16948F-011Tube96Contact BDTIC
MC74HC4046ADTR2GActivePb-free Halide freeTSSOP-16948F-011Tape and Reel2500Contact BDTIC
NLV74HC4046ADR2GActiveAEC Qualified PPAP Capable Pb-free Halide freeSOIC-16751B-051Tape and Reel2500$0.264
NLVHC4046ADTR2GActiveAEC Qualified PPAP Capable Pb-free Halide freeTSSOP-16948F-011Tape and Reel2500$0.264
Specifications
ProductInput LevelOutput LevelfMax Typ (MHz)VCC Typ (V)Duty Cycle (%)
MC74HC4046ADGCMOSCMOS3650
MC74HC4046ADR2GCMOSCMOS3650
MC74HC4046ADTGCMOSCMOS3650
MC74HC4046ADTR2GCMOSCMOS3650
NLV74HC4046ADR2GCMOSCMOS3650
NLVHC4046ADTR2GCMOSCMOS3650
Phase-Locked Loop (169kB) MC74HC4046A
Configuring and Applying the MC74HC4046A Phase-Locked Loop MC74HC4046A
SOIC 16 LEAD MC14504B
TSSOP-16 MC14504B