NB100ELT23L: Translator, Dual Differential LVPECL to LVTTL

The NB100ELT23L is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the ELT23L makes it ideal for applications which require the translation of a clock and a data signal.The ELT23L is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the ELT23L does not require both ECL standard versions. The LVPECL inputs are differential. Therefore, the NB100ELT23L can accept any standard differential LVPECL input referenced from a VCC of +3.3 V.

Features
  • 2.1 ns Typical Propagation Delay
  • Maximum Operating Frequency > 275 MHz
  • 24 mA LVTTL Outputs
  • Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
  • Open Input Default State
  • Q Output Will Default LOW with Inputs Open or at GND
Benefits
  • Precision Edge Placement
Applications
  • Clock Signal Level Translations
End Products
  • Logic Systems
Application Notes (10)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
Translator, Dual Differential LVPECL to LVTTLNB100ELT23L/D (78kB)12
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for NB100ELT23LDT 3.3VNB100ELT23LDT_33.IBS (8.0kB)1
IBIS Model for nb100elt23ld 3.3VNB100ELT23LD_33.IBS (9.0kB)2
Package Drawings (2)
Document TitleDocument ID/SizeRevision
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB100ELT23LDGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
NB100ELT23LDR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500Contact BDTIC
NB100ELT23LDTGActivePb-free Halide freeTSSOP-8948R-023Tube100$2.5333
NB100ELT23LDTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
Specifications
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
NB100ELT23LDG2ECLTTL3.31601.91700 1250
NB100ELT23LDR2G2ECLTTL3.31601.91700 1250
NB100ELT23LDTG2ECLTTL3.31601.91700 1250
NB100ELT23LDTR2G2ECLTTL3.31601.91700 1250
Translator, Dual Differential LVPECL to LVTTL (78kB) NB100ELT23L
AC Characteristics of ECL Devices NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for NB100ELT23LDT 3.3V NB100ELT23L
IBIS Model for nb100elt23ld 3.3V NB100ELT23L
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L