NB100LVEP221: Clock / Data Fanout Buffer, 2:1:20 Differential, HSTL / ECL / PECL, 2.5 V / 3.3 V

The NB100LVEP221 is a low skew 2:1:20 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential ECL/PECL; CLK1/CLK1bar can also receive HSTL signal levels. The LVPECL input signals can be either differential or single-ended (if the VBB output is used).The LVEP221 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.To ensure tightest skew, both sides of differential outputs should be terminated identically into 50 ohms even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.The NB100LVEP221, as with most other ECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVEP221 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on PECL terminations, designers should refer to Application Note AND8020/D.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.Single-ended CLK input operation is limited to VCC >/= 3.0 V in LVPECL mode, or VEE

Features
  • 15 ps Typical Output-to-Output Skew
  • 40 ps Typical Device-to-Device Skew
  • Jitter Less than 2 ps RMS
  • Maximum Frequency > 1.0 Ghz Typical
  • VBB Output
  • 540 ps Typical Propagation Delay
  • LVPECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V
  • Q Output will Default Low with Inputs Open or at VEE
Applications
  • Multiple Clock Sources
Application Notes (13)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5V/3.3V 2:1:20 Differential HSTL/ECL/PECL Clock DriverNB100LVEP221/D (129kB)10
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for NB100LVEP221FA at 2.5 VNB100LVEP221FA_25.IBS (7.0kB)0
IBIS Model for nb100lvep221fa 3.3VNB100LVEP221FA_33.IBS (7.0kB)3
Package Drawings (2)
Document TitleDocument ID/SizeRevision
8X8MM 0.5MM PITCH485M (60.8kB)C
LQFP 52 LEAD EXPOSED PAD 10x10848H-01 (78.3kB)B
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB100LVEP221FAGLast ShipmentsPb-free Halide freeLQFP-52848H-013Tray JEDEC160
NB100LVEP221FARGLast ShipmentsPb-free Halide freeLQFP-52848H-013Tape and Reel1500
NB100LVEP221MNGActivePb-free Halide freeQFN-52485M2Tray JEDEC260Contact BDTIC
NB100LVEP221MNRGActivePb-free Halide freeQFN-52485M2Tape and Reel2000Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB100LVEP221MNGBuffer12:1:20CML HSTL ECL LVDSECL3.3 2.51500.54 0.593001000
NB100LVEP221MNRGBuffer12:1:20CML LVDS ECL HSTLECL2.5 3.31500.54 0.593001000
2.5V/3.3V 2:1:20 Differential HSTL/ECL/PECL Clock Driver (129kB) NB100LVEP221
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for NB100LVEP221FA at 2.5 V NB100LVEP221
IBIS Model for nb100lvep221fa 3.3V NB100LVEP221
LQFP 52 LEAD EXPOSED PAD 10x10 NB100LVEP222
8X8MM 0.5MM PITCH NB4L7210