NB3N121K: Clock / Data Fanout Buffer, 1:21 Differential, 3.3 V, with HCSL Outputs

The NB3N121K is a differential 1:21 Clock and Data fanout buffer with High-speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N121K is designedwith HCSL PCI Express clock distribution and FBDIMM applications in mind.

Features

Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and400 MHz
340 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
100 ps Max Within Device Skew
150 ps Max DevicetoDevice Skew
Delta-tpd 100 ps Maximum Propagation Delay Variation Per Each Differential Pair
0.1 ps Typical RMS Additive Phase Jitter
LVDS Output Levels Optional with Interface Termination
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
Typical HCSL Output Level (700 mV PeaktoPeak)

Applications

Clock Distribution
PCIe I, II, III
Networking
High End Computing
Routers

End Products

Servers

Application Notes (6)

Document Title	Document ID/Size	Revision	Revision Date
Board Level Application Notes for DFN and QFN Packages	AND8211/D (175.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
How To Use Thermal Data Found in Data Sheets	AND8220/D (208.0kB)	0
Semiconductor Package Thermal Characterization	AND8215/D (363.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016

Package Drawings (1)

Document Title	Document ID/Size	Revision
8X8MM 0.5MM PITCH	485M (60.8kB)	C

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
Fanout Clock Driver, 3.3 V Differential in 1:21 Differential, with HCSL Outputs	NB3N121K/D (130.0kB)	1

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
NB3N121KMNG	Active	Pb-free Halide free	QFN-52	485M	1	Tray JEDEC	260	Contact BDTIC
NB3N121KMNR2G	Active	Pb-free Halide free	QFN-52	485M	1	Tape and Reel	2000	Contact BDTIC