NB3N51044: Clock Generator, 3.3 V, Crystal to 100 MHz / 125MHz, Quad HCSL / LVDS

The NB3N51044 is a precision, low phase noise clock generator that supports PCI Express and sRIO clock requirements. The device accepts a 25 MHz fundamental mode parallel resonant crystal or a 25 MHz single ended reference clock signal and generates four differential HCSL/LVDS outputs of 100 MHz or 125 MHz clock frequency based on frequency select input F_SEL. NB3N51044 is configurable to bypass the PLL from signal path using BYPASS, and provides the output frequency through the divider network. All clock outputs can be individually enabled / disabled through hardware input pins OE. In addition, device can be reset using Master Reset input pin MR_OE#.

Features
  • Output frequency selection of 100 MHz or 125 MHz
  • Typical Phase Jitter @ 125 MHz (integrated 1.875 MHz to 20 MHz): 0.2 ps
  • Typical Cycle-cycle Jitter @ 100 MHz (10k cycles): 20 ps
  • Uses 25 MHz Fundamental Crystal or Reference Clock Input
  • Four Low Skew HCSL or LVDS Outputs
  • Individual OE Tri-states Output
  • Master Reset and BYPASS modes
  • PCIe Gen 1, Gen 2, Gen 3 Compliant
  • Operating Supply Voltage Range 3.3 V ± 5%
  • Industrial Temperature Rangeˆ-40°C to +85°C
Benefits
  • PCIe and sRIO compliant
  • Best in Class Jitter Performance
  • Best in Class Jitter Performance
Applications
  • Networking
  • Consumer
  • Computing and Peripherals
  • Industrial Equipment
  • PCIe Clock Generation Gen 1, Gen 2 and Gen 3
End Products
  • Switch and Router
  • Set Top Box, LCD TV
  • Servers, Desktop Computers
  • Automated Test Equipment
Application Notes (1)
Document TitleDocument ID/SizeRevisionRevision Date
A System Designer's Guide for Building a PCIe Clock Tree while Addressing Timing ChallengesAND9202/D (179kB)1Mar, 2015
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V, Crystal to 100 MHz / 125 MHz Quad HCSL / LVDS Clock GeneratorNB3N51044/D (129kB)1
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB3N51044 IBIS ModelNB3N51044.ibs (95kB)0Aug, 2015
Package Drawings (1)
Document TitleDocument ID/SizeRevision
28 Lead TSSOP948AA (65.5kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB3N51044DTGActivePb-free Halide freeTSSOP-28948AA1Tube50Contact BDTIC
NB3N51044DTR2GActivePb-free Halide freeTSSOP-28948AA1Tape and Reel2500Contact BDTIC
Specifications
ProductInput LevelOutput LevelVS Typ (V)fin Typ (MHz)fout Typ (MHz)tJitter(Cy-Cy) Typ (ps)tJitter(Period) Typ (ps)tJitter(Φ) Typ (ps)tR & tF Typ (ps)tR & tF Max (ps)TA Min (°C)TA Max (°C)
NB3N51044DTGCrystal CMOSLVDS HCSL3.325100 125200.4-4085
NB3N51044DTR2GCMOS CrystalHCSL LVDS3.325125 100200.4-4085
3.3 V, Crystal to 100 MHz / 125 MHz Quad HCSL / LVDS Clock Generator (129kB) NB3N51044
A System Designer's Guide for Building a PCIe Clock Tree while Addressing Timing Challenges NCN2612B
NB3N51044 IBIS Model NB3N51044
28 Lead TSSOP NCN8024