NB3N853501E: Input Mux - 2:1, LVTTL / LVCMOS, 3.3 V, Fanout Buffer - 1:4 LVPECL

The NB3N853501E is a low skew 3.3 V supply 2:1:4 clock distribution fanout buffer. An Input MUX selects one of two LVCMOS/LVTTL CLK lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using LVCMOS/LVTTL levels. A CLK_EN pin can enable or disable the outputs synchronously to eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable outputs, LOW to disable output).

Features
  • Four differential LVPECL Outputs
  • Operating range: VCC = 3.3 5% V( 3.135 to 3.465 V)
  • Two Selectable LVCMOS/LVTTL CLOCK Inputs
  • Up to 266 MHz Clock Operation
  • Output to Output Skew: 30 ps
  • Device to Device Skew 250 ps (Max.)
  • Propagation Delay 1.9 ns (Max.)
  • Additive Phase Jitter, RMS: 0.023 ps (Typ)
  • Industrial Temp. Range (40C to 85C)
Benefits
  • Multiple copies of the Clock
  • Ensures operation in the majority of designs
Applications
  • Teleconmmunications
  • Networking
  • Computing Systems
  • SONET/SDH
End Products
  • LAN/WAN
  • Enterprise Servers
  • ATE
  • Test and Measurement
Application Notes (8)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
How To Use Thermal Data Found in Data SheetsAND8220/D (208.0kB)0
Semiconductor Package Thermal CharacterizationAND8215/D (363.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Package Drawings (1)
Document TitleDocument ID/SizeRevision
TSSOP-20 WB948E-02 (39.7kB)D
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V LVTTL/LVCMOS 2:1 MUX to1: 4 LVPECL Fanout BufferNB3N853501E/D (217.0kB)2
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB3N853501EDTGActivePb-free Halide freeTSSOP-20948E-021Tube75Contact BDTIC
NB3N853501EDTR2GActivePb-free Halide freeTSSOP-20948E-021Tape and Reel2500Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB3N853501EDTGBuffer12:1:4LVCMOS LVTTLLVPECL3.30.06230700266
NB3N853501EDTR2GBuffer12:1:4LVTTL LVCMOSLVPECL3.30.06230700266
3.3 V LVTTL/LVCMOS 2:1 MUX to1: 4 LVPECL Fanout Buffer (217.0kB) NB3N853501E
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
How To Use Thermal Data Found in Data Sheets NGTB15N60EG
Semiconductor Package Thermal Characterization NGTB15N60EG
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
TSSOP-20 WB NLSX3018
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