NB4L16M: Translator, 2.5 V / 3.3 V, 5 Gb/s Multi Level, Clock/Data Input to CML, Driver / Receiver / Buffer, with Internal Termination

The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, LVCMOS/LVTTL and produce 400 mV CML output. The device is housed in a 3x3 mm 16 pin QFN package.Differential inputs incorporate internal 50 Ω termination resistors and accept LVPECL (Positive ECL), LVTTL/LVCMOS, CML, or LVDS. The differential 16 mA CML output provides matching internal 50 Ω termination, and 400 mV output swing when externally receiver terminated, 50 Ω to VCC. These features provide transmission line termination on chip, at the receiver and driver end, eliminating any use of additional external components. The VBB, an internally generated voltage supply, is available to this device only. For single ended input configuration, the unused complementary differential input is connected to VBB as a switching reference voltage. The VBB reference output can be used also to re-bias capacitor coupled differential or single ended output signals. For the capacitor coupled input signals, VBB should be connected to the VTD pin and bypassed to ground with a 0.01 µF capacitor. When not used VBB should be left open.

Features
  • Maximum Input Clock Frequency > 3.5 GHz Typical
  • Maximum Input Data Frequency > 5 Gb/s Typical
  • 220 ps Typical Propagation Delay
  • 65 ps Typical Rise and Fall Times
  • CML Output with Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
  • CML Output Level (400 mV Peak-to-Peak Output), Differential Output Only
  • 50 Ω Internal Input and Output Termination Resistors
  • Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices
  • Pb-Free Packages are Available
Applications
  • OC-3 to OC-48 SONET/SDH Data Buffering
  • 3.2Gb/s XAUI Data Buffering
Application Notes (9)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output StructureAND8173/D (144.0kB)3
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN16 3x3, 0.5P485AE (32.1kB)C
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
ECLinPS Plus SPICE Modeling KitAND8009 (343.0kB)11
Evaluation Board Documents (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB4L16MMNEVB Evaluation Board User's Manual for NB4L16MEVBUM2069/D (142.0kB)1
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
Translator, 2.5 V / 3.3 V, 5 Gb/s Multi Level, Clock/Data Input to CML, Driver / Receiver / Buffer, with Internal TerminationNB4L16M/D (767kB)4Aug, 2016
Evaluation/Development Tool Information
ProductStatusComplianceShort Description
NB4L16MMNEVBActiveTranslator with Internal Termination Evaluation Board
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB4L16MMNGActivePb-free Halide freeQFN-16485AE1Tube123Contact BDTIC
NB4L16MMNR2GActivePb-free Halide freeQFN-16485AE1Tape and Reel3000Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB4L16MMNGSignal Driver11:1CMOS TTL ECL LVDS CMLCML3.3 2.50.2100.2659035005000
NB4L16MMNR2GSignal Driver11:1CMOS TTL CML LVDS ECLCML3.3 2.50.2100.2659035005000
Translator, 2.5 V / 3.3 V, 5 Gb/s Multi Level, Clock/Data Input to CML, Driver / Receiver / Buffer, with Internal Termination (767kB) NB4L16M
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
Interfacing with ECLinPS NB100LVEP91
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output Structure NB6L295M
Termination of ECL Logic Devices NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
ECLinPS Plus SPICE Modeling Kit NB4N840M
EVBUM2069/D - 142 NB4L16MMNEVB
QFN16 3x3, 0.5P NLAS4783B