NB4N11M: Multi Level Clock / Data Input to CML Receiver / Buffer / Translator, 2.5 Gbps, 3.3 V

The NB4N11M is a differential 1−to−2 clock/data distribution/translation chip with CML output structure, targeted for high−speed clock/data applications. The device is functionally equivalent to the EP11, LVEP11, SG11 or 7L11M devices. The device produces two identical differential output copies of clock or data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such, NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications.Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS. The CML outputs are 16 mA open collector which requires resistor (RL) load path to VTT termination voltage. The open collector CML outputs must be terminated to VTT at power up. Differential outputs produces current mode logic (CML) compatible levels when receiver loaded with 50 Ω or 25 Ω loads connected to 1.8 V, 2.5 V or 3.3 V supplies. This simplifies device interface by eliminating a need for coupling capacitors.

Features
  • Maximum Input Clock Frequency > 2.5 GHz
  • Maximum Input Data Rate > 2.5 Gb/s
  • Typically 1 ps of RMS Clock Jitter
  • Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, RL = 25 Ω
  • 420 ps Typical Propagation Delay
  • 150 ps Typical Rise and Fall Times
  • Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V and VTT = 1.8 V to 3.6 V
  • Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and GigaComm Devices
  • These are Pb-Free Devices
Applications
  • Clock distribution in high speed networking and Automated Test Equipment.
Application Notes (4)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output StructureAND8173/D (144.0kB)3
Package Drawings (1)
Document TitleDocument ID/SizeRevision
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
ECLinPS Plus SPICE Modeling KitAND8009 (343.0kB)11
IBIS Model for nb4n11mNB4N11M.IBS (53.0kB)1
Evaluation Board Documents (2)
Document TitleDocument ID/SizeRevisionRevision Date
NB4N11MDTEVB Evaluation Board User's Manual for NB4N11MEVBUM2071/D (260.0kB)1
NB4N11MDTEVB Gerber Layout Files (Zip Format)NB4N11MDTEVB_GERBER (426.0kB)0
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ TranslatorNB4N11M/D (223.0kB)1
Evaluation/Development Tool Information
ProductStatusComplianceShort Description
NB4N11MDTEVBActiveClock/Data Input Evaluation Board
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB4N11MDTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
NB4N11MDTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB4N11MDTGBuffer11:2LVPECL LVTTL LVDS CML LVCMOSCML3.31250.4230025002500
NB4N11MDTR2GBuffer11:2LVPECL LVCMOS CML LVTTL LVDSCML3.31250.4230025002500
3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator (223.0kB) NB4N11M
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output Structure NB6L295M
ECLinPS Plus SPICE Modeling Kit NB4N840M
IBIS Model for nb4n11m NB4N11M
EVBUM2071/D - 260 NB4N11MDTEVB
NB4N11MDTEVB GERBER - 426 NB4N11MDTEVB
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L