NB6L11: Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V Multilevel Input to 1:2 Differential LVPECL / LVNECL

The NB6L11 is an enhanced differential 1:2 clock or data fan-out buffer/translator. The device has the same pin-out and is functionally equivalent to the LVEL11, EP11 and LVEP11 devices. Moreover, the device is optiminzed for the systems that require LOW skew, LOW jitter and LOW power consumtion.Differential input can be configured to accept single-ended signal by applying an external reference voltage to unused complementary input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS, CML or LVDS. The outputs are 800mV ECL signals.

Features

Input Clock Frequency 6 GHz
Input Data Rate 6 Gb/s
Low 14 mA Typical Power Supply Current
150 ps Typical Proagation Delay
5 ps Typical Witin Device Skew
75 ps Typical Rise/Fall Times
PECL Mode Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
Open Input Default State
Q Outputs will default LOW with Inputs Open or at VEE

Applications

Backplane Clock distribution
Signal Translation Between LVDS, CML, LVTTL or LVCMOS to LVPECL

Application Notes (15)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Max (SiGe) SPICE Modeling Kit	AND8157/D (129.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
Clock or Data Fanout Buffer / Translator, 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2	NB6L11/D (322.0kB)	9

Simulation Models (1)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Models for nb6l11d (2.5V and 3.3V)	NB6L11D.IBS (36.0kB)	3

Package Drawings (2)

Document Title	Document ID/Size	Revision
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
NB6L11DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	Contact BDTIC
NB6L11DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	Contact BDTIC
NB6L11DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	Contact BDTIC
NB6L11DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	Contact BDTIC

Specifications

Product	Type	Channels	Input / Output Ratio	Input Level	Output Level	VCC Typ (V)	tJitterRMS Typ (ps)	tskew(o-o) Max (ps)	tpd Typ (ns)	tR & tF Max (ps)	fmaxClock Typ (MHz)	fmaxData Typ (Mbps)
NB6L11DG	Buffer	1	1:2	CML LVDS ECL CMOS TTL	ECL	3.3 2.5	0.2	15	0.15	120	6000	6000
NB6L11DR2G	Buffer	1	1:2	TTL CMOS CML LVDS ECL	ECL	3.3 2.5	0.2	15	0.15	120	6000	6000
NB6L11DTG	Buffer	1	1:2	CMOS CML ECL LVDS TTL	ECL	3.3 2.5	0.2	15	0.15	120	6000	6000
NB6L11DTR2G	Buffer	1	1:2	CML CMOS TTL ECL LVDS	ECL	3.3 2.5	0.2	15	0.15	120	6000	6000