NB6L11: Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V Multilevel Input to 1:2 Differential LVPECL / LVNECL

The NB6L11 is an enhanced differential 1:2 clock or data fan-out buffer/translator. The device has the same pin-out and is functionally equivalent to the LVEL11, EP11 and LVEP11 devices. Moreover, the device is optiminzed for the systems that require LOW skew, LOW jitter and LOW power consumtion.Differential input can be configured to accept single-ended signal by applying an external reference voltage to unused complementary input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS, CML or LVDS. The outputs are 800mV ECL signals.

Features
  • Input Clock Frequency 6 GHz
  • Input Data Rate 6 Gb/s
  • Low 14 mA Typical Power Supply Current
  • 150 ps Typical Proagation Delay
  • 5 ps Typical Witin Device Skew
  • 75 ps Typical Rise/Fall Times
  • PECL Mode Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
  • Open Input Default State
  • Q Outputs will default LOW with Inputs Open or at VEE
Applications
  • Backplane Clock distribution
  • Signal Translation Between LVDS, CML, LVTTL or LVCMOS to LVPECL
Application Notes (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Max (SiGe) SPICE Modeling KitAND8157/D (129.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
Clock or Data Fanout Buffer / Translator, 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2NB6L11/D (322.0kB)9
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Models for nb6l11d (2.5V and 3.3V)NB6L11D.IBS (36.0kB)3
Package Drawings (2)
Document TitleDocument ID/SizeRevision
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB6L11DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
NB6L11DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500Contact BDTIC
NB6L11DTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
NB6L11DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB6L11DGBuffer11:2CML LVDS ECL CMOS TTLECL3.3 2.50.2150.1512060006000
NB6L11DR2GBuffer11:2TTL CMOS CML LVDS ECLECL3.3 2.50.2150.1512060006000
NB6L11DTGBuffer11:2CMOS CML ECL LVDS TTLECL3.3 2.50.2150.1512060006000
NB6L11DTR2GBuffer11:2CML CMOS TTL ECL LVDSECL3.3 2.50.2150.1512060006000
Clock or Data Fanout Buffer / Translator, 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 (322.0kB) NB6L11
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Max (SiGe) SPICE Modeling Kit NB6N14S
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Models for nb6l11d (2.5V and 3.3V) NB6L11
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L