NB6L16: Clock / Data Receiver / Driver / Translator Buffer, 2.5 V / 3.3 V Multilevel Input to Differential LVPECL/LVNECL

The NB6L16 is a high precision, low power ECL differential clock or data receiver/driver/translator buffer. The device is functionally equivalent to the EL16, EP16, LVEL16 and NBSG16 devices. With output transition times of 70 ps, it is ideally suited for high frequency, low power systems. The device is targeted for Backplane buffering, GbE clock/data distribution, Fibre Channel distribution and SONET clock/data distribution applications.Input accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are 800 mV ECL signals.The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

Features
  • Input Clock Frequency 6 GHz
  • Input Data Rate Frequency 6 Gb/s
  • Low 12 mA Typical Power Supply Current
  • 70 ps Typical Rise/Fall Times
  • 130 ps Input Propagation Delay
  • On-Chip Reference for ECL Single-Ended Input - VBB Output
  • PECL Mode Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 with VEE = 2.375 V to 3.465 V
  • Open Input Default State
  • LVDS, LVPECL, LVNECL, LVCMOS, LVTTL and CML Input Compatible
  • Low-power Clock Buffering for Power constrained PC Add-on cards
Applications
  • Backplane Data buffering
  • Signal Translation Between LVDS, CML, LVTTL or LVCMOS to LVPECL
Application Notes (14)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Max (SiGe) SPICE Modeling KitAND8157/D (129.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
Clock or Data Receiver / Driver / Translator Buffer, 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECLNB6L16/D (261kB)9Aug, 2016
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for nb6l16d (2.5V and 3.3V)NB6L16D.IBS (35.0kB)1
Package Drawings (2)
Document TitleDocument ID/SizeRevision
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB6L16DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
NB6L16DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500Contact BDTIC
NB6L16DTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
NB6L16DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB6L16DGSignal Driver11:1TTL LVDS ECL CML CMOSECL3.3 2.50.20.1312060006000
NB6L16DR2GSignal Driver11:1CML ECL LVDS TTL CMOSECL3.3 2.50.20.1312060006000
NB6L16DTGSignal Driver11:1CML TTL LVDS CMOS ECLECL2.5 3.30.20.1312060006000
NB6L16DTR2GSignal Driver11:1TTL CML CMOS LVDS ECLECL2.5 3.30.20.1312060006000
Clock or Data Receiver / Driver / Translator Buffer, 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL (261kB) NB6L16
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Max (SiGe) SPICE Modeling Kit NB6N14S
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for nb6l16d (2.5V and 3.3V) NB6L16
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L