NB7L111M: Clock / Data Driver, 2:1:10 Differential, 6.125 Gbps, 2.5 V / 3.3 V, with CML Output

The NB7L111M is a low skew 2:1:10 differential clock/data driver, designed with clock/data distribution in mind. It accepts two clock/data sources into multiplexer input and reproduces ten identical CML differential outputs. This device is ideal for clock/data distribution across the backplane or a board, and redundant clock switchover applications. The input signals can be either differential or single-ended (if the external reference voltage is provided). Differential inputs incorporate internal 50 Ohm termination resistors and accept Negative ECL (NECL), Positive ECL (PECL), LVCMOS, LVTTL, CML, or LVDS (using appropriate power supplies). The differential 16 mA CML output provides matching internal 50 Ohm termination, and 400 mV output swing when externally terminated 50 Ohm to VCC. The NB7L111M operates from a 2.5 V +/-5% supply or a 3.3 V +/- 5% supply and is guaranteed over the full industrial temperature range of -40C to +85C. This device is packaged in a low profile 8x8 mm, QFN−52 package with 0.5 mm pitch (see package dimension on the back of the datasheet). Application notes, models, and support documentation are available at www.onsemi.com.

Features

Maximum Input Clock Frequency > 5.5 GHz Typical
Maximum Input Data Rate > 6.125 Gb/s Typical
< 0.5 ps Maximum Clock RMS Jitter
< 15 ps Maximum Data Dependent Jitter at 3.125 Gb/s
50 ps Typical Rise and Fall Times
240 ps Typical Propagation Delay
2 ps Typical Duty Cycle Skew
10 ps Typical Within Device Skew
15 ps Typical Device-to-Device Skew
Operating Range: 2.5 V ±5% and 3.3 V ±5%
400 mV Differential CML Output Swing
50 Ω Internal Input and Output Termination Resistors
Pb-Free Packages are Available

Applications

SATA, PCI Express Gen2 4xFC & GbE Data Fan-out
Precision Clock Distribution / Switchover

Application Notes (14)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
GigaComm (SiGe) SPICE Modeling Kit	AND8077/D (157kB)	6
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output Structure	AND8173/D (144.0kB)	3
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

Package Drawings (1)

Document Title	Document ID/Size	Revision
8X8MM 0.5MM PITCH	485M (60.8kB)	C

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
2.5V / 3.3V, 6.125Gb/s 2:1:10 Differential Clock / Data Driver with CML Output	NB7L111M/D (187kB)	7	Apr, 2015

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
NB7L111MMNG	Active	Pb-free Halide free	QFN-52	485M	1	Tray JEDEC	260	Contact BDTIC
NB7L111MMNR2G	Active	Pb-free Halide free	QFN-52	485M	1	Tape and Reel	2000	Contact BDTIC

Specifications

Product	Type	Channels	Input / Output Ratio	Input Level	Output Level	VCC Typ (V)	tJitterRMS Typ (ps)	tskew(o-o) Max (ps)	tpd Typ (ns)	tR & tF Max (ps)	fmaxClock Typ (MHz)	fmaxData Typ (Mbps)
NB7L111MMNG	Buffer	1	2:1:10	LVDS ECL CMOS CML TTL	CML	2.5 3.3	0.2	20	0.34 0.24	75		6000
NB7L111MMNR2G	Buffer	1	2:1:10	CMOS LVDS ECL TTL CML	CML	2.5 3.3	0.2	20	0.24 0.34	75		6000