NB7L111M: Clock / Data Driver, 2:1:10 Differential, 6.125 Gbps, 2.5 V / 3.3 V, with CML Output

The NB7L111M is a low skew 2:1:10 differential clock/data driver, designed with clock/data distribution in mind. It accepts two clock/data sources into multiplexer input and reproduces ten identical CML differential outputs. This device is ideal for clock/data distribution across the backplane or a board, and redundant clock switchover applications. The input signals can be either differential or single-ended (if the external reference voltage is provided). Differential inputs incorporate internal 50 Ohm termination resistors and accept Negative ECL (NECL), Positive ECL (PECL), LVCMOS, LVTTL, CML, or LVDS (using appropriate power supplies). The differential 16 mA CML output provides matching internal 50 Ohm termination, and 400 mV output swing when externally terminated 50 Ohm to VCC. The NB7L111M operates from a 2.5 V +/-5% supply or a 3.3 V +/- 5% supply and is guaranteed over the full industrial temperature range of -40C to +85C. This device is packaged in a low profile 8x8 mm, QFN−52 package with 0.5 mm pitch (see package dimension on the back of the datasheet). Application notes, models, and support documentation are available at www.onsemi.com.

Features
  • Maximum Input Clock Frequency > 5.5 GHz Typical
  • Maximum Input Data Rate > 6.125 Gb/s Typical
  • < 0.5 ps Maximum Clock RMS Jitter
  • < 15 ps Maximum Data Dependent Jitter at 3.125 Gb/s
  • 50 ps Typical Rise and Fall Times
  • 240 ps Typical Propagation Delay
  • 2 ps Typical Duty Cycle Skew
  • 10 ps Typical Within Device Skew
  • 15 ps Typical Device-to-Device Skew
  • Operating Range: 2.5 V ±5% and 3.3 V ±5%
  • 400 mV Differential CML Output Swing
  • 50 Ω Internal Input and Output Termination Resistors
  • Pb-Free Packages are Available
Applications
  • SATA, PCI Express Gen2 4xFC & GbE Data Fan-out
  • Precision Clock Distribution / Switchover
Application Notes (14)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
GigaComm (SiGe) SPICE Modeling KitAND8077/D (157kB)6
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output StructureAND8173/D (144.0kB)3
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Package Drawings (1)
Document TitleDocument ID/SizeRevision
8X8MM 0.5MM PITCH485M (60.8kB)C
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5V / 3.3V, 6.125Gb/s 2:1:10 Differential Clock / Data Driver with CML OutputNB7L111M/D (187kB)7Apr, 2015
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB7L111MMNGActivePb-free Halide freeQFN-52485M1Tray JEDEC260Contact BDTIC
NB7L111MMNR2GActivePb-free Halide freeQFN-52485M1Tape and Reel2000Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB7L111MMNGBuffer12:1:10LVDS ECL CMOS CML TTLCML2.5 3.30.2200.34 0.24756000
NB7L111MMNR2GBuffer12:1:10CMOS LVDS ECL TTL CMLCML2.5 3.30.2200.24 0.34756000
2.5V / 3.3V, 6.125Gb/s 2:1:10 Differential Clock / Data Driver with CML Output (187kB) NB7L111M
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
GigaComm (SiGe) SPICE Modeling Kit NBSG86A
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output Structure NB6L295M
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
8X8MM 0.5MM PITCH NB4L7210