SB3N551: Clock / Data Fanout Buffer, 1:4, 3.3 V, with CMOS Outputs
The SB3N551 is a low skew 1-to 4 clock fanout buffer, designed for clock distribution in mind. The NB3N551 specifically guarantees low output-to-output skew. Optimal design, layout and processing minimize skew within a device and from device to device. The output enable (OE) pin three-states the outputs when low.
Features- Input/Output clock frequency up to 160 MHz
- Low Skew Ouptuts (250ps)
- Output Enable puts device in three-state mode
- Operating Range: VDD = 3.0 V to 5.25V
- Full Industrial Temperature Range 8-pin SOIC
- Full RoHS certification
| Benefits- Multiply the low frequency output of inexpensive crystals to the full system frequency
- Minimize timing deviations and synchronization issues
- Creates a high impedance output with no logic low or logic high value
- Ensures operation in the majority of designs
- Small package with robust thermal capability
- Meets all green international materials standards
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Applications- Clock fan out in routers, switches and other networking applications
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Data Sheets (1)
Package Drawings (1)
Order Information
| Product | Status | Compliance | Package | MSL* | Container | Budgetary Price/Unit |
|---|
| SB3N551DG | Active | Pb-free
Halide free | SOIC-8 | 751-07 | 1 | Tube | 98 | Contact BDTIC |
| SB3N551DR2G | Active | Pb-free
Halide free | SOIC-8 | 751-07 | 1 | Tape and Reel | 2500 | Contact BDTIC |
Specifications
| Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
|---|
| SB3N551DG | Buffer | 1 | 1:4 | CMOS | CMOS | 3.3
5 | 2 | 250 | 3 | 1000 | 160 | |
| SB3N551DR2G | Buffer | 1 | 1:4 | CMOS | CMOS | 5
3.3 | 2 | 250 | 3 | 1000 | 160 | |
