SH7750R
| Part Name | Order | Program Memory (KB) | RAM (KB) | Operating Voltage Min (V) |
|---|---|---|---|---|
| HD6417750RBG240 | contact | 0.0 | 0.0 | 3.0 |
| HD6417750RBG200D | contact | 0.0 | 0.0 | 3.0 |
| HD6417750RBA240H | contact | 0.0 | 0.0 | 3.0 |
| HD6417750RF240D | contact | 0.0 | 0.0 | 3.0 |
| HD6417750RF240 | contact | 0.0 | 0.0 | 3.0 |
| HD6417750RF200D | contact | 0.0 | 0.0 | 3.0 |
| HD6417750RF200 | contact | 0.0 | 0.0 | 3.0 |
| HD6417750RBP240D | contact | 0.0 | 0.0 | 3.0 |
| HD6417750RBP240 | contact | 0.0 | 0.0 | 3.0 |
| HD6417750RBP200D | contact | - | - | - |
| HD6417750RBP200 | contact | 0.0 | 0.0 | 3.0 |
| HD6417750RBG240D | contact | 0.0 | 0.0 | 3.0 |
| HD6417750RBG200 | contact | 0.0 | 0.0 | 3.0 |
The SH7750R is a 32-bit RISC (reduced instruction set computer) microprocessor, featuring object code upward-compatibility with SH-1, SH-2, and SH-3 microcomputers. It includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation look aside buffer). The SH7750R has a 16-kbyte instruction cache and a 32-kbyte data cache. The SH7750R has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.
